TW200501363A - Semiconductor die package with increased thermal conduction - Google Patents
Semiconductor die package with increased thermal conductionInfo
- Publication number
- TW200501363A TW200501363A TW093110854A TW93110854A TW200501363A TW 200501363 A TW200501363 A TW 200501363A TW 093110854 A TW093110854 A TW 093110854A TW 93110854 A TW93110854 A TW 93110854A TW 200501363 A TW200501363 A TW 200501363A
- Authority
- TW
- Taiwan
- Prior art keywords
- substrate
- metal cap
- semiconductor die
- thermal conduction
- die package
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/32—Holders for supporting the complete device in operation, i.e. detachable fixtures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01087—Francium [Fr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/438,968 US6787896B1 (en) | 2003-05-15 | 2003-05-15 | Semiconductor die package with increased thermal conduction |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200501363A true TW200501363A (en) | 2005-01-01 |
TWI239615B TWI239615B (en) | 2005-09-11 |
Family
ID=32927436
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW093110854A TWI239615B (en) | 2003-05-15 | 2004-04-19 | Semiconductor die package with increased thermal conduction |
Country Status (6)
Country | Link |
---|---|
US (1) | US6787896B1 (zh) |
JP (1) | JP4570610B2 (zh) |
KR (1) | KR100778209B1 (zh) |
CN (1) | CN1791976A (zh) |
TW (1) | TWI239615B (zh) |
WO (1) | WO2004105127A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI387061B (zh) * | 2005-11-15 | 2013-02-21 | Intel Corp | 半導體封裝體抗震增強技術 |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7224059B2 (en) * | 2003-10-21 | 2007-05-29 | Intel Corporation | Method and apparatus for thermo-electric cooling |
US7250327B2 (en) * | 2004-06-30 | 2007-07-31 | Intel Corporation | Silicon die substrate manufacturing process and silicon die substrate with integrated cooling mechanism |
JP2006024755A (ja) * | 2004-07-08 | 2006-01-26 | Fujitsu Ltd | 回路基板 |
US20060044765A1 (en) * | 2004-09-01 | 2006-03-02 | Infowize Technologies Corporation | Heat dissipation device |
US20060186535A1 (en) * | 2005-02-23 | 2006-08-24 | Visteon Global Technologies, Inc. | Semi-conductor die mount assembly |
DE102005013762C5 (de) * | 2005-03-22 | 2012-12-20 | Sew-Eurodrive Gmbh & Co. Kg | Elektronisches Gerät und Verfahren zur Bestimmung der Temperatur eines Leistungshalbleiters |
US20080140801A1 (en) * | 2006-10-05 | 2008-06-12 | Holt John M | Multiple computer system with dual mode redundancy architecture |
US8021931B2 (en) * | 2006-12-11 | 2011-09-20 | Stats Chippac, Inc. | Direct via wire bonding and method of assembling the same |
US7561430B2 (en) * | 2007-04-30 | 2009-07-14 | Watlow Electric Manufacturing Company | Heat management system for a power switching device |
US8112884B2 (en) * | 2007-10-08 | 2012-02-14 | Honeywell International Inc. | Method for providing an efficient thermal transfer through a printed circuit board |
FR2972850B1 (fr) * | 2011-03-17 | 2013-11-15 | Valeo Sys Controle Moteur Sas | Circuit électronique a double couche isolante et son procédé de fabrication |
JP5788854B2 (ja) * | 2012-11-15 | 2015-10-07 | シライ電子工業株式会社 | 回路基板 |
US9123780B2 (en) * | 2012-12-19 | 2015-09-01 | Invensas Corporation | Method and structures for heat dissipating interposers |
US9585240B2 (en) * | 2013-10-24 | 2017-02-28 | Qorvo Us, Inc. | Advanced grounding scheme |
JP6026391B2 (ja) * | 2013-11-28 | 2016-11-16 | 京セラドキュメントソリューションズ株式会社 | 過電流防止装置 |
US9536808B1 (en) | 2015-06-16 | 2017-01-03 | Macronix International Co., Ltd. | Photo pattern method to increase via etching rate |
JP6900947B2 (ja) * | 2018-12-28 | 2021-07-14 | 株式会社村田製作所 | 高周波モジュールおよび通信装置 |
US11758697B2 (en) * | 2019-09-26 | 2023-09-12 | Ohio State Innovation Foundation | Low inductance power module with vertical power loop structure and insulated baseplates |
CN111863626B (zh) * | 2020-06-28 | 2021-12-07 | 珠海越亚半导体股份有限公司 | 支撑框架结构及其制作方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05160289A (ja) * | 1991-12-10 | 1993-06-25 | Fujitsu Ltd | 半導体チップの実装構造 |
KR0124788B1 (ko) * | 1994-06-16 | 1997-11-26 | 황인길 | 반도체 패키지용 구리산화물-충진 폴리머 다이 어태치 접착제 조성물 |
JPH09205044A (ja) * | 1996-01-26 | 1997-08-05 | Tokin Corp | チップ部品の製造方法 |
JP3194035B2 (ja) * | 1996-04-22 | 2001-07-30 | 日本ミクロン株式会社 | 電子部品用パッケージの製造方法 |
JPH10308471A (ja) * | 1997-05-07 | 1998-11-17 | Akita Denshi Kk | 混成集積回路装置およびその製造方法 |
US6160705A (en) * | 1997-05-09 | 2000-12-12 | Texas Instruments Incorporated | Ball grid array package and method using enhanced power and ground distribution circuitry |
US6201701B1 (en) * | 1998-03-11 | 2001-03-13 | Kimball International, Inc. | Integrated substrate with enhanced thermal characteristics |
JP3216626B2 (ja) * | 1999-01-20 | 2001-10-09 | 日本電気株式会社 | 増幅装置 |
JP4480818B2 (ja) * | 1999-09-30 | 2010-06-16 | 株式会社ルネサステクノロジ | 半導体装置 |
US6477054B1 (en) * | 2000-08-10 | 2002-11-05 | Tektronix, Inc. | Low temperature co-fired ceramic substrate structure having a capacitor and thermally conductive via |
-
2003
- 2003-05-15 US US10/438,968 patent/US6787896B1/en not_active Expired - Lifetime
-
2004
- 2004-04-06 KR KR1020057019439A patent/KR100778209B1/ko active IP Right Grant
- 2004-04-06 CN CNA2004800132397A patent/CN1791976A/zh active Pending
- 2004-04-06 JP JP2006501257A patent/JP4570610B2/ja not_active Expired - Lifetime
- 2004-04-06 WO PCT/US2004/010753 patent/WO2004105127A1/en active Application Filing
- 2004-04-19 TW TW093110854A patent/TWI239615B/zh active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI387061B (zh) * | 2005-11-15 | 2013-02-21 | Intel Corp | 半導體封裝體抗震增強技術 |
Also Published As
Publication number | Publication date |
---|---|
KR100778209B1 (ko) | 2007-11-22 |
WO2004105127B1 (en) | 2005-02-24 |
CN1791976A (zh) | 2006-06-21 |
WO2004105127A1 (en) | 2004-12-02 |
KR20060009842A (ko) | 2006-02-01 |
TWI239615B (en) | 2005-09-11 |
JP4570610B2 (ja) | 2010-10-27 |
US6787896B1 (en) | 2004-09-07 |
JP2006525653A (ja) | 2006-11-09 |
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