TWI387061B - 半導體封裝體抗震增強技術 - Google Patents

半導體封裝體抗震增強技術 Download PDF

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TWI387061B
TWI387061B TW095141876A TW95141876A TWI387061B TW I387061 B TWI387061 B TW I387061B TW 095141876 A TW095141876 A TW 095141876A TW 95141876 A TW95141876 A TW 95141876A TW I387061 B TWI387061 B TW I387061B
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package
core
circuit board
terminal
elastic material
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Rahul N Manepalli
Sairam Agraharam
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Intel Corp
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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Description

半導體封裝體抗震增強技術 發明背景
本發明係概括有關半導體封裝。
半導體封裝體通常利用銲球被連接至一主機板。此等封裝體應該要能夠承受譬如運送期間所可能發生之衝震及振動。
銲球通常係藉由形成間金屬化合物(IMC’s)而被銲接至封裝體引線。這些IMC’s通常很脆且在衝震及振動條件下會容易經歷斷裂。因為無鉛銲料及無鉛銲料所形成的IMC’s通常皆比目前有鉛銲料更具勁性且更脆，所以在無鉛銲料及無鉛封裝體技術之案例中尤其如此。
並且，由於需要縮小裝置及增加裝填密度，銲球的尺寸與間距係持續減小。較小的銲球導致了銲接點中與衝震及振動相關的失效之較高危險。
依據本發明之一實施例，係特地提出一種方法，包含：提供一具有一終端之彈性材料以緩衝衝震負荷。
依據本發明之一實施例，係特地提出一種半導體封裝體，包含：一結構；一終端，其耦合至該結構；及一彈性材料，其位於該結構與該終端之間。
依據本發明之一實施例，係特地提出一種系統，包含：一電路板；及一經封裝積體電路，其電性耦合至該電路板，該經封裝積體電路係包括終端，一封裝體結構，及一位於該等終端與該封裝體結構之間的彈性材料。
圖式簡單說明
第1圖為根據本發明的一實施例之一封裝體的放大部分橫剖視圖；第2圖為根據本發明的一實施例位於一印刷電路板上定位之封裝體的放大部分橫剖視圖；第3圖為處於製造的一早期階段之對應於第1圖的放大部分橫剖視圖；第4圖為根據本發明的一實施例處於製造的一後續階段之對應於第3圖的放大部分橫剖視圖；第5圖為根據本發明的一實施例處於製造的一後續階段之對應於第4圖的放大部分橫剖視圖；第6圖為根據本發明的一實施例處於第5圖所示者的一後續階段之放大部分橫剖視圖；第7圖為根據本發明的一實施例處於一後續階段之放大部分橫剖視圖；第8圖為根據本發明的一實施例處於一後續階段之放大部分橫剖視圖；及第9圖為一實施例之系統描繪。
 詳細描述
參照第1圖，一半導體封裝體65在一實施例中可為一晶片級封裝體(CSP)。晶片級封裝體係為一不大於原始晶粒面積的1.2倍之單晶粒、可直接表面安裝式封裝體。舉例而言，一晶片級封裝體可為一覆晶片、非覆晶片、打線接合、球柵陣列或有引線式封裝體。
封裝體65可包括一穿設有導縫48之核心18。導縫48可為有襯墊式、無襯墊式、無插塞式、或有插塞式。一實施例中，核心18可為一具有經鑽製導縫48之經鑽製核心。封裝體65亦可為任何封裝體類型，包括具有並非銲球的電性終端之封裝體。其他終端可為金屬性終端，舉例而言，包括針腳、插塞及插座等。
一諸如處理器等積體電路82可被安裝在核心18上方。電路82可經由封裝體65電性耦合至位於封裝體的相對側上之終端。一實施例中，這些終端可為銲球16。一實施例中，電路82可經由打線結合部79及結合墊81電性耦合至封裝體65。
在一CSP實施例中，金屬物36及32嵌夾住核心18。一實施例中，金屬物32及36可由銅形成。金屬物36具有開口46，開口46在一實施例中係對準於導縫48。金屬物32具有開口52，開口52在一實施例中可至少部分地不對準於導縫48。一實施例中，開口52係大於導縫48故使其在至少一側上之核心18一部分底下重疊於延伸部53處。
部分實施例中，導縫48可充填有一金屬襯墊或插塞(未圖示)。然而，部分實施例中，可不使用襯墊或插塞。一黏彈性材料56可亦形成於延伸部53中。黏彈性材料56基於下文所說明的用途可具有低的楊氏模數(Young’s modulus)。
一銲阻劑58可位於金屬物層32底下。銲阻劑58中可形成一充填有一接觸部42之開口。接觸部42可對於導縫48襯墊或對於一未顯示於第1圖的金屬物產生電性連接。
銲球16可被表面安裝至接觸部42。因此，可經由核心18至銲球16產生電性連接。
封裝體65的任何衝震負荷皆可被黏彈性材料56所緩衝。特定言之，銲球16上且特別是位於一往上方向之任何衝震係將接觸部42驅迫至用以減振衝震負荷之黏彈性材料56中。則實質上，黏彈性材料56係作為一用以緩衝銲球16上的任何過度衝震負載之彈簧。
接著參照第2圖，封裝體65可安裝在一諸如印刷電路板等電路板70上。一實施例中，電路板70可具有一下層76及一上層74，其以標點狀設有經嵌入接觸部72。銲球16可被表面安裝至接觸部72上。因此，經由電路板70施加至銲球16之任何衝震負載皆可被封裝體65中及部分實施例中的電路板70內等兩者之黏彈性材料56所緩衝。
根據本發明的一實施例之第1圖所示的結構65之製造方法係顯示於第3至8圖中。起初，核心18已經被鑽製以如第3圖所示形成導縫48。並且，核心18已塗覆有上金屬物36及下金屬物32。如前述，開口46及52可容許經由核心18及部分案例中經過導縫48之電性導通。因此，一實施例中，銅金屬物32、36可形成於導縫48的任一側上。如第4圖所示，開口52的一延伸部53係延伸於一側上之核心18底下。
如第4圖所示，以開口O對準於延伸部53利用一模板S來模板印刷一順應性層藉以充填延伸部53。然後，如第5圖所示，一黏彈性材料56可經由模板S開口O列印在延伸部53內。
接著，如第6圖所示，可施加一銲阻劑58。銲阻劑58可被曝光及顯影以形成經曝光區60。區60隨後可被移除以形成開口61(第7圖)且充填有一金屬以形成接觸部42，如第8圖所示。易言之，開口61係充填有金屬接觸部42，如第8圖所示。一實施例中，用於接觸部42之金屬可為一鎳、金合金。接觸部42對於一金屬物(未圖示)產生電性連接。其後，銲球16可被表面安裝至接觸部42上。所產生的結構顯示於第1圖中。
可藉由黏彈性材料56來緩衝在掉落及衝震測試中展現出高失效率的無鉛銲球之細微間距式球柵陣列封裝體。此等失效的主要模式可能係為銲球與一基材或主機板的表面光製之間的脆性間金屬。隨著晶片級封裝體中的間距減小及球數增加，此失效模式變得更差而未被矯正，導致互連部斷開及組件的災難性失效。
藉由黏彈性材料56，利用順應性層可易於消散衝震負載，故降低對於球體/介面之能量轉移。部分實施例中，一類似的順應性層可施加至主機板側上，如第2圖所示，藉以容許進一步的衝震減振。易言之，黏彈性材料56亦可連同電路板70使用。
對於實行一衝震能量減振及能量轉移降低而言，用於材料56之順應性層的選擇係很重要。此外，所選用材料可能與基材製造程序相容。材料的一特徵係可能為具有高的能量正切或高的能量模數作為對應於衝震負荷之頻率。此應用可使用之典型材料係包括具有經過調節可在衝震頻率處具有高損失正切的分子量之矽氧，矽氧經修改環氧樹脂，或聚醯亞胺樹脂及低分子量橡膠諸如羧基終止式丁二烯丙烯腈(CTBN)。一般而言，黏彈性材料56可有利地在室溫下具有小於約3兆帕斯卡(gagaPascals)的楊氏模數。
參照第9圖，描繪根據本發明的一實施例之一以處理器為基礎的系統80。該系統在一實施例中可為一以處理器為基礎的系統。因此，舉例而言，系統80可為一電腦、膝上型電腦、桌上型電腦、伺服器、媒體播放器、可攜式裝置、或數位攝影機。
部分實施例中，系統80可包括一處理器82。處理器82在一實施例中可由封裝體65實行。處理器102可耦合至一作為一電路板70之主機板。電路板70可包括處理器82，且連帶具有一匯流排84。
額外的積體電路可耦合至電路板70。以處理器為基礎的系統之常見組件的範例係包括一輸入/輸出(I/O)介面81，一靜態隨機存取記憶體(SRAM)90，及一系統記憶體88，其在部分實施例中可由動態隨機存取記憶體(DRAM)實行。當然，系統80的架構係具有顯著的變異性且亦可包括有廣泛不同的其他組件。
此說明書中提及“一項實施例”或“一實施例”時係指連同該實施例所描述的一特定特性、結構或特徵被包括在本發明所涵蓋的至少一實行方式中。因此，出現“一項實施例”或“一實施例中”未必指同一實施例。尚且，可以所顯示的特定實施例以外的其他適當形式來設計特定的特性、結構或特徵，且所有此等形式皆可被涵蓋於本申請案的申請專利範圍內。
雖然已經就有限數量的實施例來描述本發明，熟習該技術者將自其瞭解許多的修改及變異。申請專利範圍預定涵蓋落在本發明的真實精神及範圍內之所有此等修改及變異。
16．．．銲球
18．．．核心
32．．．下金屬物
36．．．上金屬物
42．．．金屬接觸部
46,52,61,O．．．開口
48．．．導縫
53．．．延伸部
56．．．黏彈性材料
58．．．銲阻劑
60．．．經曝光區
65．．．半導體封裝體,結構
70．．．電路板
72．．．經嵌入接觸部
74．．．上層
76．．．下層
79．．．打線結合部
80．．．以處理器為基礎的系統
81．．．結合墊,輸入/輸出(I/O)介面
82．．．積體電路
84．．．匯流排
88．．．系統記憶體
90．．．靜態隨機存取記憶體(SRAM)
102．．．處理器
S．．．模板
第1圖為根據本發明的一實施例之一封裝體的放大部分橫剖視圖；第2圖為根據本發明的一實施例位於一印刷電路板上定位之封裝體的放大部分橫剖視圖；第3圖為處於製造的一早期階段之對應於第1圖的放大部分橫剖視圖；第4圖為根據本發明的一實施例處於製造的一後續階段之對應於第3圖的放大部分橫剖視圖；第5圖為根據本發明的一實施例處於製造的一後續階段之對應於第4圖的放大部分橫剖視圖；第6圖為根據本發明的一實施例處於第5圖所示者的一後續階段之放大部分橫剖視圖；第7圖為根據本發明的一實施例處於一後續階段之放大部分橫剖視圖；第8圖為根據本發明的一實施例處於一後續階段之放大部分橫剖視圖；及第9圖為一實施例之系統描繪。
16．．．銲球
18．．．核心
32．．．下金屬物
36．．．上金屬物
42．．．金屬接觸部
46,52．．．開口
48．．．導縫
53．．．延伸部
56．．．黏彈性材料
58．．．銲阻劑
65．．．半導體封裝體，結構
79．．．打線結合部
81．．．結合墊，輸入/輸出(I/O)介面
82．．．積體電路

Claims (7)

  1. 一種半導體封裝體，其包含：一結構，其具有一核心，在該核心的兩側中之任一側上有金屬層，其中該核心包括數個經鑽製開孔且該等金屬層包括數個開孔，位於該等金屬層中之一者中的該等開孔延伸出該核心中之該等開孔以形成一延伸部；耦合至該結構的一終端；位於該結構與該終端之間的一彈性材料；以及位於該彈性材料與該終端之間的一接觸部。
  2. 如申請專利範圍第1項之封裝體，其中該封裝體為一晶片級封裝體。
  3. 如申請專利範圍第1項之封裝體，其中該終端為一銲球。
  4. 如申請專利範圍第1項之封裝體，其中該彈性材料具有在室溫下小於3兆帕斯卡的楊氏模數。
  5. 如申請專利範圍第1項之封裝體，其進一步附接至一電路板。
  6. 如申請專利範圍第5項之封裝體，其中該電路板包括一彈性材料，且該終端及該封裝體係電性固接至該電路板。
  7. 如申請專利範圍第1項之封裝體，其中該彈性材料位於該延伸部中。
TW095141876A 2005-11-15 2006-11-13 半導體封裝體抗震增強技術 TWI387061B (zh)

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CN101310383B (zh) 2012-04-25
KR20080058487A (ko) 2008-06-25

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