CN101310383B - 增强半导体封装件的耐震性 - Google Patents

增强半导体封装件的耐震性 Download PDF

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CN101310383B
CN101310383B CN2006800423141A CN200680042314A CN101310383B CN 101310383 B CN101310383 B CN 101310383B CN 2006800423141 A CN2006800423141 A CN 2006800423141A CN 200680042314 A CN200680042314 A CN 200680042314A CN 101310383 B CN101310383 B CN 101310383B
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terminal
elastomeric material
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R·N·曼帕利
S·阿格拉哈拉姆
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Abstract

加于焊球的震动负荷可通过与焊球一起提供粘弹性材料而得以减缓。该粘弹性材料可减弱加于焊球的震动负荷并降低焊球与封装件其余部分之间的失效率。

Description

增强半导体封装件的耐震性
技术领域
本发明一般地涉及半导体封装件。
背景技术
半导体封装件一般通过使用焊球与母板连接。这样的封装件应该经得起如运输途中发生的冲撞与振动。焊球一般通过形成金属间化合物(IMC)的方式焊接到封装引线上。这些IMC一般非常脆,容易在受到冲撞与振动时破碎。在无铅焊料和无铅封装工艺中尤为如此,因为无铅焊料和由无铅焊料形成的IMC一般都比现用的含铅焊料更硬而更脆。
而且,出于装置小型化和提高封装密度的需要,焊球的尺寸和间距在不断减少。较小的焊球会导致较高的冲撞与振动风险,而这关系到焊接点的失效。
附图说明
图1为表示本发明一个实施例的封装件的局部剖视放大图。
图2为表示本发明一个实施例的印刷电路板上的封装件的局部剖视放大图。
图3为对应于图1的制造开始阶段的局部剖视放大图。
图4为本发明一个实施例的对应于图3的后续制造阶段的局部剖视放大图。
图5为本发明一个实施例的对应于图4的后续制造阶段的局部剖视放大图。
图6为本发明一个实施例的图5之后的阶段的局部剖视放大图。
图7为本发明一个实施例的后续阶段的局部剖视放大图。
图8为本发明一个实施例的后续阶段的局部剖视放大图。
图9表示一个实施例的系统。
发明内容
参见图1,在一个实施例中半导体封装件65可以是一种芯片级封装件(CSP)。芯片级封装件是单裸片的、面积仅为原裸片的1.2倍的直接表面安装的封装件。芯片级封装例如可以是倒装片、非倒装片、线焊、球栅阵列或引脚封装等。
封装件65可包括一个其中有通路48贯穿而延伸的芯层18。通路48可以是带衬套的、不带衬套的、无塞的或有塞的。在一个实施例中,芯层18可以是带钻孔通路48的钻孔芯层。封装件65也可为任何封装型式,包含具有不同于焊球的电端子的封装。其它端子例如可以是含有销、塞和插孔的金属端子。
安装在芯层18之上的可以是例如处理器那样的集成电路82。该电路82可以穿过封装件65与封装件对面的端子电性连接。在一个实施例中,这些端子可以是焊球16。在一个实施例中,电路82可以通过焊线79和焊盘81与封装件65电性连接。
在一个CSP实施例中,芯层18夹在金属镀敷层36和32之间。在一个实施例中,金属镀敷层36和32可由铜形成。在一个实施例中,金属镀敷层36具有对准通路48的开口46。在一个实施例中,金属镀敷层32具有可至少部分地不对准通路48的开口52。在一个实施例中,开口52大于通路48,以致它们至少在一侧在芯层18的一部分之下的扩展部53处搭接。
在一些实施例中,通路48内可填入金属衬或金属塞(未图示)。然而,在一些实施例中,可不使用衬套或塞。也可在扩展部53上形成粘弹性材料56。该粘弹性材料56可具有低的杨氏模量,以达成后述之目的。
金属镀敷层32之下可为阻焊层58。阻焊层58上可以有其中嵌入接触部42的开口。接触部42可实现与通路48的衬套(若有的话)的电性连接,或可与图1中未示出的金属镀敷层电性连接。
焊球16可表面安装到接触部42上。这样,可穿过芯层18而到达焊球16来实现电性连接。
封装件65的任何震动负荷可由粘弹性材料56缓冲。特别地,焊球上的任何震动,尤其是上向的震动,推动接触部42进入能衰减震动负荷的粘弹性材料56。实际上,粘弹性材料56起到弹簧的作用,缓冲了作用于焊球16的过度的震动负荷。
接着参阅图2,封装件65可安装在如印刷电路板那样的电路板70上。在一个实施例中,线路板70可以有下层76和上层74,上层74中点状地嵌有接触部72。焊球16可表面安装在接触部72上。这样,任何通过电路板70而加到焊球16上的震动负荷可由封装件65内和一些实施例中电路板70内的粘弹性材料56进行缓冲。
图3-8表示按照本发明的一个实施例的图1所示结构65的制造方法。最初,如图3所示,芯层18被钻孔而形成通路48。此外,芯层18还覆盖了上金属镀敷层36和下金属镀敷层32。如已指出,在一些场合开口46和52能够实现经通路48穿过芯层18的电性连接。这样,在一个实施例中可在通路48的两侧形成铜镀敷层32、36。如图4所示,开口52的扩展部53在芯层18之下的一侧扩展。
如图4所示,扩展部53由使用带对准其的开口O的模版S进行印刷来填入。然后,如图5所示,粘弹性材料56可以通过模版S的开口O印到扩展部53上。
接着如图6所示,可施加阻焊层58。阻焊层58可被曝光并显影而形成曝光区域60。该区域60然后可被除去而形成开口61(图7),并如图8所示填入金属而形成接触部42。换句话说,图8所示的开口61以填入金属接触部42。在一个实施例中,接触部42的金属可以是镍金合金。接触部42可与金属镀敷层形成电性连接(未图示)。此后,焊球16可表面安装到接触部42上。最终的结构如图1所示。
在跌落和震动试验中呈现高失效率的带无铅焊球的小节距球栅阵列封装件可因粘弹性材料56而得到缓冲。这种失效的主要方式可能是焊球与基板或母板的表面层之间的易碎的金属间化合物。随着芯片级封装件中节距的减少和焊球数的增加,这种失效方式会变得更严重而难以补救,导致互连开路和元件的突然失效。
使用粘弹性材料56,震动负荷容易被顺从层分散,因此减小了对球面/界面的能量传递。在一些实施例中,如图2所示,可在母板侧使用一种类似的顺从层,从而可进一步减震。换句话说,粘弹性材料56也可与电路板70结合使用。
顺从层材料56的选择对于衰减震动能量和减少能量传递的影响很大。此外,被选材料可与基板的制造工艺相适应。该材料的一个特性可为在频率对应于震动负荷时具有高的损耗因数或高的损耗模量。可作此用途的典型材料包括可调整分子量以便在震动频率下具有高损耗因数的硅树脂、硅改性环氧树脂或者聚酰亚胺树脂和诸如端羧基丁腈橡胶(CTBN)等低分子量橡胶。大概而言,室温下具有小于3000兆帕左右的杨氏模量的粘弹性材料是有利的。
图9说明根据本发明的一个实施例的基于处理器的系统80。该系统可以是一个实施例中的一个基于处理器的系统。因而,该系统80例如可以是计算机、膝上型计算机、桌上型计算机、服务器、媒体播放机、便携式设备或数码相机。
在一些实施例中,系统80可以包括处理器82。在一个实施例中,处理器82可由封装件65来实现。处理器102可连接到充当电路板70的母板上。电路板70可包括处理器82以及总线84。
线路板70上可连接附加的集成电路。基于处理器的系统通常的部件例如包括输入/输出(I/O)接口81、静态随机存取存储器(SRAM)90和系统内存88,在一些实施例中后者可用动态随机存取存储器(DRAM)实现。当然,系统80的体系结构可以作相当大的改变,也可包括多种多样的其它部件。
本说明书通篇提到的“一个实施例”或“一实施例”表示与该实施例有关的特征、结构或特性包括在本发明所含的至少一个实施方式中,因而,“在一个实施例中”或“在一实施例中”的短语之出现不必涉及同一实施例。此外,这些特征、结构或特性可以以其它不同于所阐明的特定实施例的合适形式建立,所有这样的形式可包括在本申请的权利要求书的范围内。
尽管本发明已描述了有限个实施例本领域技术人员会由此领悟到许多改进和变化。后附的权利要求书旨在覆盖所有落入本发明真实精神和范围的改进和变化。

Claims (19)

1.一种用于制造半导体封装件的方法,其中包括:
形成芯层,所述芯层的两面有金属层,所述芯层包含若干钻孔,所述金属层也包含若干孔;
扩展所述金属层之一中的孔而超过所述芯层中的孔,从而形成扩展部;
在所述扩展部中提供弹性材料,所述弹性材料具有端子并用于减缓震动负荷;以及
在所述弹性材料与所述端子之间形成接触部。
2.如权利要求1所述的方法,其中,包括在所述接触部上表面安装焊球形式的端子。
3.如权利要求1所述的方法,其中,包括形成包含所述材料的芯片级封装件。
4.如权利要求3所述的方法,其中,包括在电路板上安装所述芯片级封装件。
5.如权利要求4所述的方法,其中,包括设置具有接触部的电路板并在所述接触部上表面安装焊球。
6.如权利要求4所述的方法,其中,包括在所述电路板中的所述接触部之下设置所述材料。
7.一种半导体封装件,其中包括:
封装结构,其具有芯层,所述芯层的两面有金属层,所述芯层包含若干钻孔,所述金属层也包含若干孔,所述金属层之一中的孔扩展而超过所述芯层中的孔,从而形成扩展部;
与所述结构连接的端子;以及
在所述结构与所述端子之间的弹性材料。
8.如权利要求7所述的半导体封装件,其中,所述封装件是一种芯片级封装件。
9.如权利要求7所述的半导体封装件,其中,所述端子是焊球。
10.如权利要求7所述的半导体封装件,其中,所述弹性材料在室温下具有小于3000兆帕的杨氏模量。
11.如权利要求7所述的半导体封装件,进而被安装到电路板上。
12.如权利要求11所述的半导体封装件,其中,所述电路板包含一种弹性材料,所述端子和所述封装件被电性固定在所述电路板上。
13.如权利要求7所述的半导体封装件,其中,所述弹性材料在所述扩展部内。
14.如权利要求13所述的半导体封装件,其中,包括位于所述弹性材料与所述端子之间的接触部。
15.一种用于增强耐震性的系统,其中包括:
电路板;以及
与所述电路板电性连接的经封装的集成电路,所述经封装的集成电路包含端子、封装结构以及位于所述端子与所述封装结构之间的弹性材料,
其中所述封装结构具有芯层,所述芯层的两面有金属层,所述芯层包含若干钻孔,所述金属层也包含若干孔,所述金属层之一中的孔扩展而超过所述芯层中的孔,从而形成扩展部。
16.如权利要求15所述的系统,其中,所述经封装的集成电路是处理器。
17.如权利要求15所述的系统,其中,包括所述电路板中的弹性材料。
18.如权利要求15所述的系统,其中,所述弹性材料在室温下具有小于3000兆帕的杨氏模量。
19.如权利要求15所述的系统,其中,所述端子是焊球。
CN2006800423141A 2005-11-15 2006-11-14 增强半导体封装件的耐震性 Expired - Fee Related CN101310383B (zh)

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Families Citing this family (1)

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Publication number Priority date Publication date Assignee Title
CN104766835B (zh) * 2015-04-15 2017-07-28 苏州聚达晟芯微电子有限公司 一种低温抗震的半导体封装结构

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1220774A (zh) * 1997-03-21 1999-06-23 精工爱普生株式会社 半导体装置、薄膜载带及其制造方法
US5983492A (en) * 1996-11-27 1999-11-16 Tessera, Inc. Low profile socket for microelectronic components and method for making the same
US6348741B1 (en) * 2000-02-23 2002-02-19 Hitachi, Ltd. Semiconductor apparatus and a manufacturing method thereof

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3961092B2 (ja) * 1997-06-03 2007-08-15 株式会社東芝 複合配線基板、フレキシブル基板、半導体装置、および複合配線基板の製造方法
CN1161838C (zh) * 1997-10-17 2004-08-11 伊比登株式会社 封装基板
US6465744B2 (en) * 1998-03-27 2002-10-15 Tessera, Inc. Graded metallic leads for connection to microelectronic elements
US6177728B1 (en) * 1998-04-28 2001-01-23 International Business Machines Corporation Integrated circuit chip device having balanced thermal expansion
US6181219B1 (en) * 1998-12-02 2001-01-30 Teradyne, Inc. Printed circuit board and method for fabricating such board
JP3792445B2 (ja) * 1999-03-30 2006-07-05 日本特殊陶業株式会社 コンデンサ付属配線基板
US6407927B1 (en) * 1999-08-31 2002-06-18 International Business Machines Corporation Method and structure to increase reliability of input/output connections in electrical devices
US6399896B1 (en) * 2000-03-15 2002-06-04 International Business Machines Corporation Circuit package having low modulus, conformal mounting pads
JP2002057252A (ja) * 2000-08-07 2002-02-22 Hitachi Ltd 半導体装置及びその製造方法
JP3640876B2 (ja) * 2000-09-19 2005-04-20 株式会社ルネサステクノロジ 半導体装置及び半導体装置の実装構造体
TW517360B (en) * 2001-12-19 2003-01-11 Ind Tech Res Inst Enhanced type wafer level package structure and its manufacture method
US6826830B2 (en) * 2002-02-05 2004-12-07 International Business Machines Corporation Multi-layered interconnect structure using liquid crystalline polymer dielectric
US6787896B1 (en) * 2003-05-15 2004-09-07 Skyworks Solutions, Inc. Semiconductor die package with increased thermal conduction

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5983492A (en) * 1996-11-27 1999-11-16 Tessera, Inc. Low profile socket for microelectronic components and method for making the same
CN1220774A (zh) * 1997-03-21 1999-06-23 精工爱普生株式会社 半导体装置、薄膜载带及其制造方法
US6348741B1 (en) * 2000-02-23 2002-02-19 Hitachi, Ltd. Semiconductor apparatus and a manufacturing method thereof

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
同上.

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TW200807642A (en) 2008-02-01
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WO2007059191A1 (en) 2007-05-24
US7718904B2 (en) 2010-05-18
KR20080058487A (ko) 2008-06-25
US20070111375A1 (en) 2007-05-17
CN101310383A (zh) 2008-11-19

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