200409288 玖、發明說明： 【發明所屬之技術領域】 本發明係關於半導體裝置及其製造方法，尤其是關於在 形成電容器洞（capacity hole)時的電容量控制。 【先前技術】 參照圖4所示，針對習知半導體裝置之製造方法進行說 明。 圖4所示係習知半導體裝置之製造方法的說明剖視圖。 詳言之，圖4 ( a )所示係電容器洞形成前的狀態圖，圖4 ( b ) 所示係電容器洞形成後的狀態圖，圖4 ( c )係終止膜去除後 的狀態圖，圖4 ( d )係形成電容器後的狀態圖。 首先，如圖4 ( a)所示，在矽基板1上形成閘極氧化膜2， 在閘極氧化膜2上形成複數個閘極3。其次，在閘極3間 的矽基板 1 上層，利用離子植入形成源極汲極區域（未圖 示）。然後，依覆蓋著閘極3之方式，在矽基板1整面上形 成氮化矽膜4。其次，在氮化矽膜4上形成第1層間絕緣 膜5。然後形成從第1層間絕緣膜5表面到達矽基板1的 栓塞1 6。 其次，在第1層間絕緣膜5與栓塞1 6上形成終止膜1 7。 其中，終止膜1 7乃具有防止電容器洞2 1 (如後述）與栓塞 1 6產生位差現象的機能。 其次，在終止膜1 7上形成第2層間絕緣膜1 8。然後， 在第2層間絕緣膜1 8上形成抗反射膜1 9及光阻圖案2 0。 其次，如圖4 ( b )所示，利用以光阻圖案2 0為罩幕的乾 6 312/發明說明書(補件)/92-10/92119795 200409288 式蝕刻處理，形成從第2層間絕緣膜1 8表面到達終止膜 1 7的電容器洞2 1。 其次，如圖4(c)所示，去除光阻圖案20與抗反射膜19。 然後，將曝露於電容器洞2 1底部外的終止膜1 7予以去除。 最後，如圖4 ( d )所示，在電容器洞2 1内形成電容器。 詳言之，在電容器洞21内形成下電極2 2，將此下電極2 2 表面粗面化，並在下電極22上形成電容器絕緣體23，再 於電容器絕緣體2 3上形成上電極2 4。 【發明内容】 (發明所欲解決之問題） 習知製造方法乃在終止膜 1 7上的第 2層間絕緣膜 1 8 内，形成電容器洞21。 所以，因為電容器的電容乃隨第 2層間絕緣膜1 8膜厚 而決定，因此無法控制電容。 本發明乃為解決上述習知問題，其目的在於輕易地控制 電容。 (解決問題之手段） 本發明的半導體裝置之製造方法，係包含有：依覆蓋著 基板上所形成複數閘極之方式，形成第1層間絕緣膜的步 驟； 形成從上述第1層間絕緣膜表面到達上述複數閘極間之 上述基板的栓塞的步驟； 在上述第1層間絕緣膜與上述栓塞上，形成終止膜的步 驟； 7 312/發明說明書(補件)/92-10/92119795 200409288 在上述終止膜上形成第2層間絕緣膜的步驟； 形成從上述第2層間絕緣膜表面貫穿上述終止膜，並在 上述第1層間絕緣膜内，底面位於較上述栓塞上面更下方 處之電容洞的步驟；以及 在上述電容洞内形成電容器的步驟， 藉由控制上述電容洞之底面位置，以控制著上述電容器 的電容。 【實施方式】 以下，參照圖式，針對本發明之實施形態進行說明。圖 中，對相同或相當部分賦予相同元件符號，並簡化或省略 說明。 首先，參照圖1所示，針對本實施形態的半導體裝置進 行說明。 圖1所示係本發明實施形態的半導體裝置之說明圖。詳 言之，圖1 ( a )所示係本實施形態之半導體裝置的剖視圖， 圖1 ( b )所示係圖1 ( a )所示半導體裝置中，電容器洞與栓塞 之位置關係的俯視圖。 如圖1所示，在基板1的石夕基板上，隔著閘極氧化膜閘 的絕緣膜2形成複數閘極3。在複數閘極3間的矽基板1 上層，形成源極汲極區域（未圖示）。 依覆蓋著閘極3之方式形成氮化矽膜4，在氮化矽膜4 上形成第1層間絕緣膜5。此第1層間絕緣膜5係膜厚5 0 0 n m 之BPTE0S膜、與其上所形成膜厚200nm之NSG膜的沉積 膜。形成從第1層間絕緣膜5表面到達閘極3間的矽基板 8 312/發明說明書(補件)/92-10/921】9795 200409288 1，且由摻雜多晶矽所構成的栓塞6。 在第1層間絕緣膜5上形成氮化矽膜的終止膜7。其中， 終止膜7乃供防止電容器洞1 1 (如後述）與栓塞6產生位差 現象，以及防止耦接於上層配線的接觸洞（未圖示）與栓塞 產生位差現象用的。 在終止膜7上形成第2層間絕緣膜8。此第2層間絕緣 膜8係膜厚1150nm之BPTE0S膜、與其上所形成膜厚250nm 之NSG膜的沉積膜。 形成從第2層間絕緣膜8表面貫穿終止膜7，且在第1 層間絕緣膜5内，底面1 1 a位於較栓塞6上面6 a更下方位 置處的電容器洞1 1。換句話說，在電容器洞1 1的底面11 a 上，依露出栓塞6上方的方式，形成電容器洞11。 再者，電容器洞1 1的底面1 1 a位置係控制在從第1層 間絕緣膜5表面到氮化矽膜4表面為止的範圍A内。換句 話說，依電容器洞1 1之底面1 1 a不致鄰接於閘極3之方 式，控制著電容器洞1 1深度。藉此控制著電容（容後述）。 再者，如圖1 (b)所示，栓塞6係位於電容器洞1 1側面 附近。 在電容器洞1 1内形成電容器。詳言之，在電容器洞1 1 側面與底面1 1 a、以及曝露出的栓塞6上面6 a與側面，形 成粗面化多晶矽膜的下電極1 2，在下電極1 2上形成氮化 矽膜的電容器絕緣體1 3，在電容器絕緣體1 3上形成非晶 矽膜的上電極1 4。 其次，針對上述半導體裝置之製造方法進行說明。 9 312/發明說明書(補件)/92-10/92〗19795 200409288 圖2所示係圖1所示半導體裝置之製造方法的說明剖視 圖。 首先，如圖2 ( a)所示，在矽基板1上形成閘極氧化膜2， 在閘極氧化膜 2上形成複數閘極3。其次，在複數閘極3 間的矽基板1上層，利用離子植入形成源極汲極區域（未圖 示）。然後，依覆蓋著閘極3之方式，在矽基板1整面上形 成氮化梦膜4。 其次，在氮化矽膜4上將BPTE0S膜形成50 Onm，並當作 第1層間絕緣膜5用，然後再於其上形成膜厚2 0 0 nm的NSG 膜。然後，形成從第1層間絕緣膜5表面到達閘極3間之 矽基板1表面的栓塞6，在第1層間絕緣膜5與栓塞6上 形成膜厚80nm氮化矽膜的終止膜7。 接著，在終止膜7上形成膜厚1150nm之BPTE0S膜的第 2層間絕緣膜8，再於其上形成膜厚2 5 0 n m的N S G膜。然後， 在第2層間絕緣膜8上形成抗反射膜（B A R C ) 9與光阻圖案 1 0 〇 其次，如圖2 ( b)所示，利用以光阻圖案1 0為罩幕的乾 式蝕刻處理，形成從第2層間絕緣膜8表面貫穿終止膜7， 且在第1層間絕緣膜5内，底面1 1 a位於栓塞6上面6 a 更下方位置處的電容器洞 1 1。詳言之，首先，利用採用 C 4 F 8、0 2、A r混合氣體的R I E電漿蝕刻處理，形成從第2 層間絕緣膜8表面到達終止膜7的電容器洞1 1。接著，利 用採用C H F 3、0 2、A r混合氣體的R I E電漿蝕刻處理，將露 出於電容器洞1 1底部外的終止膜7予以去除。然後，利用 10 312/發明說明書(補件)/92-10/929795 200409288 採用C 4 F 8、0 2、A r混合氣體的R I E電漿蝕刻處理，去除第 1層間絕緣膜5，並將電容器洞1 1朝下方延伸。此時，電 容器洞1 1底面1 1 a的位置乃控制於從第1層間絕緣膜5 表面到氮化石夕膜4表面為止的範圍A内。換句話說，依電 容器洞1 1之底面1 1 a不致鄰接於閘極3之方式，控制著電 容器洞1 1深度。藉此控制著電容（容後述）。 最後，如圖2 ( c )所示，去除光阻圖案1 0與抗反射膜9， 在電容器洞1 1内形成電容器。詳言之，依覆蓋著電容器洞 1 1側面與底面1 1 a、以及電容器洞1 1内曝露出栓塞6上面 6 a與側面之方式，形成摻雜多晶矽膜的下電極1 2，並將此 下電極1 2表面粗面化。其次，在下電極1 2上形成氮化矽 膜的電容器絕緣體1 3，在電容器絕緣體1 3上形成非晶矽 膜的上電極1 4，對電容器絕緣體1 3與上電極1 4施行圖案 化處理。 在此，因為相較於習知製造方法之下，電容器洞 1 1較 深，因此便可將此變深部分的電容器洞1 1側面、與曝露出 栓塞6側面部分，使用於電容器方面。所以，藉由電容器 洞1 1深度（即，控制電容器洞1 1的底面1 1 a位置）便可控 制電容器容量。 如上述說明，在本實施形態中，藉由將電容器洞 1 1 延 伸至第1層間絕緣膜 5内，便可增加所延長電容器洞11 側面與曝露出栓塞6側面之表面積分的電容。 所以，藉由電容器洞1 1的底面1 1 a的位置（即，控制著 第1層間絕緣膜5之蝕刻量）便可控制電容器容量。 11 312/發明說明書(補件)/92-10/92119795 200409288 再者，依照本實施形態的話，不致大幅更改習知半導體 裝置之構造與製造方法，便可控制電容器容量。 其次，參照圖 3，針對本實施形態的半導體裝置變化例 進行說明。 圖 3 所示係本發明實施形態的半導體裝置變化例說明 圖。詳言之，圖3 ( a )所示係本實施形態之半導體裝置變化 例剖視圖，圖3 ( b )所示係圖3 ( a )所示變化例中，電容器洞 與栓塞之位置關係的俯視圖。 如圖3所示，在此變化例中，栓塞6乃位於電容器洞1 1 中心附近。藉此便可將栓塞 6整個側面、與電容器洞 11 整個側面都利用為電容器。換句話說，藉由電容器洞 11 内的栓塞6位置，便可改變電容器洞1 1側面與栓塞6側面 的表面積。 所以，依照本變化例的話，除上述實施形態的效果之 外，尚能獲得可輕易增加電容的效果。 (發明效果） 依照本發明的話，可輕易地控制電容。 【圖式簡單說明】 圖1 ( a )、（ b )為本發明實施形態的半導體裝置說明圖。 圖 2(a)〜（c)為本發明實施形態的半導體裝置之製造方 法說明剖視圖。 圖 3 ( a )、（ b )為本發明實施形態的半導體裝置變化例說 明圖。 圖 4 ( a )〜（d )為習知半導體裝置之製造方法說明剖視 12 312/發明說明書(補件)/92-10/92119795 200409288 圖。 (元件符號說明） 1 基板（碎基板） 2 閘極絕緣膜（閘極氧化膜） 3 閘極 4 氮化碎膜 5 第1層間絕緣膜（BPTE0S膜、NSG膜） 6 栓塞 6 a 上面 7 終止膜（氮化矽膜） 8 第2層間絕緣膜（BPTE0S膜、NSG膜） 9 抗反射膜（BARC) 10 光阻圖案 11 電容器洞（開口部） 11a 底面 12 下電極（摻雜多晶矽膜） 13 電容器絕緣體（氮化矽膜） 14 上電極（非晶矽膜） 16 栓塞 17 終止膜 18 第2層間絕緣膜 19 抗反射膜 20 光阻圖案 2 1 電容器洞 13200409288 (1) Description of the invention: [Technical field to which the invention belongs] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to controlling capacitance when a capacitor hole is formed. [Prior Art] A method for manufacturing a conventional semiconductor device will be described with reference to FIG. 4. FIG. 4 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device. Specifically, the state diagram before the capacitor hole formation shown in FIG. 4 (a), the state diagram after the capacitor hole formation shown in FIG. 4 (b), and the state diagram after removal of the termination film are shown in FIG. 4 (c). Fig. 4 (d) is a state diagram after the capacitor is formed. First, as shown in FIG. 4 (a), a gate oxide film 2 is formed on a silicon substrate 1, and a plurality of gates 3 are formed on the gate oxide film 2. Secondly, on the silicon substrate 1 above the gate 3, a source-drain region is formed by ion implantation (not shown). Then, a silicon nitride film 4 is formed on the entire surface of the silicon substrate 1 so as to cover the gate electrode 3. Next, a first interlayer insulating film 5 is formed on the silicon nitride film 4. Then, a plug 16 is formed which reaches the silicon substrate 1 from the surface of the first interlayer insulating film 5. Next, a stopper film 17 is formed on the first interlayer insulating film 5 and the plug 16. Among them, the termination film 17 has a function of preventing a step phenomenon between the capacitor hole 2 1 (described later) and the plug 16. Next, a second interlayer insulating film 18 is formed on the termination film 17. Then, an antireflection film 19 and a photoresist pattern 20 are formed on the second interlayer insulating film 18. Next, as shown in FIG. 4 (b), a dry 6 312 / Invention Specification (Supplement) / 92-10 / 92119795 200409288 type etching process using a photoresist pattern 20 as a mask is used to form a second interlayer insulating film. 1 8 The surface reaches the capacitor hole 21 of the termination film 17. Next, as shown in FIG. 4 (c), the photoresist pattern 20 and the anti-reflection film 19 are removed. Then, the termination film 17 exposed outside the bottom of the capacitor hole 21 is removed. Finally, as shown in FIG. 4 (d), a capacitor is formed in the capacitor hole 21. Specifically, a lower electrode 22 is formed in the capacitor hole 21, the surface of the lower electrode 2 2 is roughened, a capacitor insulator 23 is formed on the lower electrode 22, and an upper electrode 24 is formed on the capacitor insulator 23. [Summary] (Problems to be Solved by the Invention) A conventional manufacturing method is to form a capacitor hole 21 in a second interlayer insulating film 1 8 on a termination film 17. Therefore, since the capacitance of the capacitor is determined by the thickness of the second interlayer insulating film 18, the capacitance cannot be controlled. The present invention is to solve the above-mentioned conventional problems, and an object thereof is to easily control the capacitance. (Means for Solving the Problem) The method for manufacturing a semiconductor device of the present invention includes the steps of forming a first interlayer insulating film by covering a plurality of gate electrodes formed on a substrate; and forming a surface from the surface of the first interlayer insulating film. The step of reaching the plug of the substrate between the plurality of gates; the step of forming a stop film on the first interlayer insulating film and the plug; 7 312 / Invention Specification (Supplement) / 92-10 / 92119795 200409288 in the above A step of forming a second interlayer insulating film on the terminating film; a step of forming a capacitor hole penetrating the terminating film from the surface of the second interlayer insulating film and in the first interlayer insulating film, the bottom surface of which is lower than the top of the plug And the step of forming a capacitor in the capacitor hole, by controlling the position of the bottom surface of the capacitor hole, to control the capacitance of the capacitor. [Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the figure, the same or corresponding parts are given the same component symbols, and the description is simplified or omitted. First, a semiconductor device according to this embodiment will be described with reference to FIG. 1. FIG. 1 is an explanatory diagram of a semiconductor device according to an embodiment of the present invention. Specifically, FIG. 1 (a) is a cross-sectional view of a semiconductor device of this embodiment, and FIG. 1 (b) is a plan view of the positional relationship between a capacitor hole and a plug in the semiconductor device shown in FIG. 1 (a). As shown in FIG. 1, a plurality of gates 3 are formed on a stone substrate of the substrate 1 through an insulating film 2 of a gate oxide film gate. A source drain region (not shown) is formed on the silicon substrate 1 between the plurality of gates 3. A silicon nitride film 4 is formed so as to cover the gate electrode 3, and a first interlayer insulating film 5 is formed on the silicon nitride film 4. This first interlayer insulating film 5 is a deposited film of a BPTE0S film having a film thickness of 500 nm and a NSG film having a film thickness of 200 nm formed thereon. A silicon substrate 8 312 / Invention Specification (Supplement) / 92-10 / 921] 9795 200409288 1 is formed from the surface of the first interlayer insulating film 5 to the gates 3, and a plug 6 made of doped polycrystalline silicon is formed. A termination film 7 of a silicon nitride film is formed on the first interlayer insulating film 5. Among them, the stopper film 7 is used to prevent the capacitor hole 11 (as described later) from forming a dislocation phenomenon with the plug 6, and to prevent the contact hole (not shown) coupled to the upper layer wiring from forming a dislocation phenomenon. A second interlayer insulating film 8 is formed on the stopper film 7. This second interlayer insulating film 8 is a deposited film of a BPTEOS film having a film thickness of 1150 nm and a NSG film having a film thickness of 250 nm formed thereon. A capacitor hole 11 is formed which penetrates the termination film 7 from the surface of the second interlayer insulating film 8 and has a bottom surface 1 1 a located at a position lower than the upper surface 6 a of the plug 6 in the first interlayer insulating film 5. In other words, the capacitor hole 11 is formed on the bottom surface 11 a of the capacitor hole 11 so as to be exposed above the plug 6. The position of the bottom surface 1 1 a of the capacitor hole 11 is controlled within a range A from the surface of the first interlayer insulating film 5 to the surface of the silicon nitride film 4. In other words, the depth of the capacitor hole 11 is controlled in such a manner that the bottom surface 1 1 a of the capacitor hole 11 does not adjoin the gate electrode 3. This controls the capacitance (to be described later). Furthermore, as shown in FIG. 1 (b), the plug 6 is located near the side of the capacitor hole 11. A capacitor is formed in the capacitor hole 11. In detail, the lower electrode 12 of the roughened polycrystalline silicon film is formed on the side and bottom surface 1 1 a of the capacitor hole 1 1 and the upper surface 6 a and the side of the exposed plug 6, and a silicon nitride film is formed on the lower electrode 12 A capacitor insulator 1 3 is formed, and an upper electrode 14 of an amorphous silicon film is formed on the capacitor insulator 13. Next, a method for manufacturing the semiconductor device will be described. 9 312 / Invention Specification (Supplement) / 92-10 / 92〗 19795 200409288 FIG. 2 is a cross-sectional view illustrating a method for manufacturing the semiconductor device shown in FIG. 1. First, as shown in FIG. 2 (a), a gate oxide film 2 is formed on a silicon substrate 1, and a plurality of gate electrodes 3 are formed on the gate oxide film 2. Next, a source drain region (not shown) is formed on the silicon substrate 1 above the plurality of gates 3 by ion implantation. Then, a silicon nitride film 4 is formed on the entire surface of the silicon substrate 1 so as to cover the gate electrode 3. Next, a BPTE0S film was formed on the silicon nitride film 4 to a thickness of 50 nm and used as the first interlayer insulating film 5, and then an NSG film having a thickness of 200 nm was formed thereon. Then, a plug 6 is formed from the surface of the first interlayer insulating film 5 to the surface of the silicon substrate 1 between the gates 3, and a stop film 7 is formed on the first interlayer insulating film 5 and the plug 6 to a thickness of 80 nm. Next, a second interlayer insulating film 8 of a BPTEOS film having a thickness of 1150 nm is formed on the stopper film 7, and an N S G film having a thickness of 250 nm is formed thereon. Then, an anti-reflection film (BARC) 9 and a photoresist pattern 100 are formed on the second interlayer insulating film 8. Next, as shown in FIG. 2 (b), a dry etching process using the photoresist pattern 10 as a mask is used. A capacitor hole 11 is formed through the termination film 7 from the surface of the second interlayer insulating film 8 and in the first interlayer insulating film 5 with a bottom surface 1 1 a located above the plug 6 6 a and further below. In detail, first, the capacitor hole 11 is formed from the surface of the second interlayer insulating film 8 to the termination film 7 by using a R I E plasma etching process using a mixed gas of C 4 F 8, 0, 2 and Ar. Next, the termination film 7 exposed from the bottom of the capacitor hole 11 is removed by using an RIE plasma etching process using a mixture of C H F 3, 0 2, and Ar. Then, using 10 312 / Invention Specification (Supplement) / 92-10 / 929795 200409288, the RIE plasma etching process using a C 4 F 8, 0, 2 A mixed gas is used to remove the first interlayer insulating film 5 and the capacitor The holes 11 extend downward. At this time, the position of the bottom surface 1 1 a of the capacitor hole 11 is controlled within a range A from the surface of the first interlayer insulating film 5 to the surface of the nitride film 4. In other words, the depth of the capacitor hole 11 is controlled in such a manner that the bottom surface 1 1 a of the capacitor hole 11 does not abut the gate 3. This controls the capacitance (to be described later). Finally, as shown in FIG. 2 (c), the photoresist pattern 10 and the anti-reflection film 9 are removed to form a capacitor in the capacitor hole 11. In detail, the lower electrode 1 2 doped with a polycrystalline silicon film is formed by covering the side and bottom surface 1 1 a of the capacitor hole 11 and exposing the upper surface 6 a and the side surface of the plug 6 inside the capacitor hole 11 1, and The surface of the lower electrode 12 is roughened. Next, a capacitor insulator 13 with a silicon nitride film formed on the lower electrode 12 and an upper electrode 14 with an amorphous silicon film formed on the capacitor insulator 13 is patterned. The capacitor insulator 13 and the upper electrode 14 are patterned. Here, since the capacitor hole 11 is deeper than the conventional manufacturing method, the deepened part of the capacitor hole 11 and the side of the exposed plug 6 can be used for capacitors. Therefore, the capacitor capacity can be controlled by the depth of the capacitor hole 11 (that is, by controlling the position of the bottom surface 1 1 a of the capacitor hole 11). As described above, in this embodiment, by extending the capacitor hole 1 1 into the first interlayer insulating film 5, the capacitance integrated on the side of the extended capacitor hole 11 and the surface of the exposed plug 6 can be increased. Therefore, the capacitor capacity can be controlled by the position of the bottom surface 1 1 a of the capacitor hole 11 (that is, the amount of etching of the first interlayer insulating film 5 is controlled). 11 312 / Invention Specification (Supplement) / 92-10 / 92119795 200409288 Furthermore, according to this embodiment, the capacitor capacity can be controlled without greatly changing the structure and manufacturing method of the conventional semiconductor device. Next, a modification of the semiconductor device according to this embodiment will be described with reference to FIG. 3. FIG. 3 is a diagram illustrating a modification of the semiconductor device according to the embodiment of the present invention. Specifically, FIG. 3 (a) is a cross-sectional view of a modified example of the semiconductor device of this embodiment, and FIG. 3 (b) is a plan view of the positional relationship between the capacitor hole and the plug in the modified example shown in FIG. 3 (a). . As shown in FIG. 3, in this modification, the plug 6 is located near the center of the capacitor hole 1 1. In this way, the entire side of the plug 6 and the entire side of the capacitor hole 11 can be used as a capacitor. In other words, by the position of the plug 6 in the capacitor hole 11, the surface area of the side of the capacitor hole 11 and the side of the plug 6 can be changed. Therefore, according to this modification, in addition to the effects of the above-mentioned embodiment, an effect that the capacitance can be easily increased can be obtained. (Effects of the Invention) According to the present invention, the capacitance can be easily controlled. [Brief Description of the Drawings] FIGS. 1 (a) and (b) are explanatory diagrams of a semiconductor device according to an embodiment of the present invention. 2 (a) to (c) are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. 3 (a) and (b) are explanatory diagrams of a modified example of a semiconductor device according to an embodiment of the present invention. Figures 4 (a) ~ (d) are cross-sectional views illustrating the manufacturing method of a conventional semiconductor device 12 312 / Invention Specification (Supplement) / 92-10 / 92119795 200409288. (Description of component symbols) 1 Substrate (Broken substrate) 2 Gate insulating film (Gate oxide film) 3 Gate 4 Nitrided chip 5 First interlayer insulating film (BPTE0S film, NSG film) 6 Plug 6 a Upper 7 Termination Film (silicon nitride film) 8 Second interlayer insulating film (BPTE0S film, NSG film) 9 Anti-reflection film (BARC) 10 Photoresist pattern 11 Capacitor hole (opening) 11a Bottom surface 12 Lower electrode (doped polycrystalline silicon film) 13 Capacitor insulator (silicon nitride film) 14 Upper electrode (amorphous silicon film) 16 Plug 17 Stop film 18 Second interlayer insulating film 19 Anti-reflection film 20 Photoresist pattern 2 1 Capacitor hole 13
312/發明說明書(補件)/92-10/92119795 200409288 2 2 下電極 23 電容器絕緣體 2 4 上電極312 / Invention Specification (Supplement) / 92-10 / 92119795 200409288 2 2 Lower electrode 23 Capacitor insulator 2 4 Upper electrode
312/發明說明書(補件)/92-10/921丨9795 14312 / Invention Specification (Supplement) / 92-10 / 921 丨 9795 14