KR100861791B1 - Method for forming the semiconductor device - Google Patents
Method for forming the semiconductor device Download PDFInfo
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- KR100861791B1 KR100861791B1 KR1020020040086A KR20020040086A KR100861791B1 KR 100861791 B1 KR100861791 B1 KR 100861791B1 KR 1020020040086 A KR1020020040086 A KR 1020020040086A KR 20020040086 A KR20020040086 A KR 20020040086A KR 100861791 B1 KR100861791 B1 KR 100861791B1
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- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 25
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 25
- 239000010703 silicon Substances 0.000 claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 claims abstract description 14
- 238000005468 ion implantation Methods 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 6
- 150000002500 ions Chemical class 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 230000006641 stabilisation Effects 0.000 abstract description 2
- 238000011105 stabilization Methods 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/27—ROM only
- H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
- H10B20/38—Doping programmed, e.g. mask ROM
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 메모리(Memory)소자의 BN 구조 형성방법에 있어서, 실리콘기판에 비등방성 식각에 의해 트랜치를 형성하여 트랜치 주변에 경사 이온주입하여 BN 정션을 형성한 후, 트랜치 내에 산화막을 매립하여 BN층을 형성하는 것을 특징으로 하는 트랜치형 BN 구조를 형성함으로써 셀 영역을 평탄하게 형성시켜 소자의 동작 속도를 증가시킬 수 있으며, BN 정션의 안정화를 향상시켜 반도체소자의 특성 및 신뢰성을 향상시키는 기술이다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, in the method of forming a BN structure of a memory device, a trench is formed on an silicon substrate by anisotropic etching to form a BN junction by inclining ion implantation around the trench. After that, by forming a trench type BN structure in which a oxide layer is buried in the trench to form a BN layer, the cell region can be flattened to increase the operation speed of the device and improve the stabilization of the BN junction. It is a technique to improve the characteristics and reliability.
BN층, BN정션, 트랜치BN floor, BN junction, trench
Description
도 1a 내지 도 1e는 종래 반도체소자의 제조방법을 설명하기 위해 순차적으로 나타낸 공정 단면도이다.1A through 1E are cross-sectional views sequentially illustrating a method of manufacturing a conventional semiconductor device.
도 2는 종래 반도체소자의 제조방법에 의해 형성된 BN 구조의 문제점을 나타낸 SEM 사진이다.2 is a SEM photograph showing the problem of the BN structure formed by the conventional method of manufacturing a semiconductor device.
도 3a 내지 도 3d는 본 발명의 실시예에 따른 반도체소자의 제조방법을 설명하기 위해 순차적으로 나타낸 공정 단면도이다.
3A through 3D are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
-- 도면의 주요부분에 대한 부호의 설명 -- -Explanation of symbols for the main parts of the drawing-
10 : 실리콘기판 20 : n-웰10: silicon substrate 20: n-well
30 : 필드산화막 40 : 절연막30: field oxide film 40: insulating film
50 : 트랜치 60 : BN 정션50: trench 60: BN junction
70 : BN층
70: BN layer
본 발명은 반도체소자의 제조방법에 관한 것으로, 보다 상세하게는 플래쉬 메모리(Flash Memory)소자의 BN 구조 형성방법에 있어서, 실리콘기판에 트랜치 기법을 사용하여 BN정션을 형성한 후, 트랜치를 매립하여 평탄한 셀 영역을 형성하도록 하는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, in a method of forming a BN structure of a flash memory device, by forming a BN junction on a silicon substrate using a trench technique, and then filling a trench. A method of manufacturing a semiconductor device for forming a flat cell region.
일반적으로, 플래쉬 이이피롬(FLASH EEPROM) 셀이나, 마스크 롬(MASK ROM)의 셀에서 사용중인 베리드 N+(Buried N+)(이하, BN 정션이라 칭함)는 버츄얼 그라운드(Virtual Ground)가 가능하고 콘택의 수를 감소시킴으로써 칩 사이즈를 감소시키는 이점이 있다.In general, the buried N + (Buried N + ) (hereinafter referred to as BN junction) used in a flash EEPROM cell or a mask ROM cell can be a virtual ground. And reducing the number of contacts has the advantage of reducing the chip size.
도 1a 내지 도 1e는 종래 반도체소자의 제조방법을 설명하기 위해 순차적으로 나타낸 공정 단면도이다.1A through 1E are cross-sectional views sequentially illustrating a method of manufacturing a conventional semiconductor device.
먼저, 도 1a에 도시된 바와 같이, p형 실리콘기판(1)에 필드산화막(3)을 형성하여 소자를 격리하는 격리영역과 소자를 형성하는 활성영역으로 정의한 후, 활성영역 내에 n-웰(2)을 형성한다.First, as shown in FIG. 1A, a
그리고, 도 1b에 도시된 바와 같이, 상기 실리콘기판(1) 상에 질화물을 약 1000Å 정도 증착하여 절연막(4)을 형성하고 절연막(4) 상부에 감광막을 도포한 후 노광 및 현상공정을 진행하여 BN층 형성영역이 개방되도록 감광막 패턴(미도시함)을 형성한다.As shown in FIG. 1B, nitride is deposited on the silicon substrate 1 by about 1000 Å to form an
이때, 상기 절연막(4)은 후속 옥시데이션 공정에 의한 BN층 형성 시, 장벽층 역할 및 BN 정션 형성을 위한 이온 주입 시, 이온주입 마스크 역할을 한다.In this case, the
이어서, 상기 감광막 패턴(미도시함)을 마스크로 하여 절연막(4)을 식각하여 실리콘기판(1)을 소정부분 노출시킨 후, 감광막 패턴(미도시함)을 제거한다.Subsequently, the
그 후, 도 1c에 도시된 바와 같이 결과물 전체에 약 800Å 정도의 두께로 산화막(미도시함)을 증착한 후, 이를 전면식각하여 절연막(4) 측벽에 산화막으로 이루어진 스페이서(5)를 형성한다.Thereafter, an oxide film (not shown) is deposited to a total thickness of about 800 GPa on the entire resultant, as shown in FIG. 1C, and then etched to form a spacer 5 made of an oxide film on the sidewall of the
그리고, 도 1d에 도시된 바와 같이 상기 절연막(4)과 스페이서(5)를 마스크로 이용하여 노출된 실리콘기판에 As 이온을 경사없이 수직으로 주입한 후, 옥시데이션 및 열처리 공정을 수행하면 실리콘기판 상에 BN층인 산화막(6)이 성장함과 동시에 이온확산에 의해 BN층 하부에 BN 정션(7)이 형성된다. 상기 BN 정션(7)은 소자의 소오스 및 드레인영역으로 사용된다.In addition, as shown in FIG. 1D, the As substrate is vertically injected without inclination into the exposed silicon substrate using the
이어서, 도 1e에 도시된 바와 같이, 상기 절연막과 스페이서를 제거함으로써, 옥시데이션에 의해 형성된 BN 구조를 형성한다.Subsequently, as illustrated in FIG. 1E, the insulating film and the spacer are removed to form a BN structure formed by oxidization.
그러나, 상기와 같은 종래 반도체소자의 제조방법에 의해 BN 구조를 형성하면, 도 2의 "A"와 같이 옥시데이션에 의해 산화막 형성 시, 버즈빅이 형성되어 셀의 CD 및 정션에 악영향을 주어 반도체소자의 특성과 신뢰성을 저하시키는 문제점이 있었다. However, if the BN structure is formed by the conventional method of manufacturing a semiconductor device as described above, when the oxide film is formed by oxidization as shown in " A " of FIG. 2, a burj bic is formed, which adversely affects the CD and the junction of the semiconductor. There was a problem of degrading the characteristics and reliability of the device.
또한, 상기 열공정 시 주입된 이온이 확산되어 형성되는 BN 정션은 "B"와 같이 상부 모서리 부분이 얇게 형성되어 셀 특성, 즉 온/오프 셀 문턱전압과 전류 및 속도 등을 저하시켜 반도체소자의 제조수율을 감소시키는 문제점이 있었다.In addition, the BN junction formed by diffusion of ions implanted in the thermal process has a thin upper edge portion, such as "B", and thus deteriorates cell characteristics, that is, on / off cell threshold voltage, current, and speed, and so on. There was a problem in reducing the production yield.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 본 발명의 목적은 메모리 소자의 BN 구조 형성방법에 있어서, 셀 영역을 평탄하게 형성시켜 소자의 동작 속도를 증가시킬 수 있으며, BN 정션의 안정화를 향상시키도록 하는 반도체소자의 제조방법을 제공하는 것이다.The present invention has been made to solve the above problems, an object of the present invention is to form a cell region in the BN structure forming method of the memory device, it is possible to increase the operating speed of the device by forming a flat cell area, the BN junction It is to provide a method for manufacturing a semiconductor device to improve the stabilization.
상기 목적을 달성하기 위하여, 본 발명은 소자분리막과 웰이 형성된 실리콘기판 상에 절연막을 형성한 후 절연막 상부에 BN층 형성 영역이 개방되도록 감광막 패턴을 형성하는 단계와, 상기 감광막 패턴을 마스크로 절연막을 오버식각하여 실리콘기판 내에 트랜치를 형성하는 단계와, 상기 절연막을 마스크로 BN 정션 형성을 위한 BN 이온을 경사 이온 주입하고 절연막을 제거하는 단계와, 상기 결과물 상에 산화막을 증착한 후 실리콘기판 상부까지 등방성 식각하여 BN층을 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 제조방법을 제공한다.In order to achieve the above object, the present invention is to form an insulating film on the silicon substrate on which the device isolation film and the well is formed, forming a photoresist pattern so that the BN layer forming region is opened on the insulating film, and the insulating film using the photoresist pattern as a mask Forming a trench in the silicon substrate by over-etching the same, implanting BN ions for forming the BN junction using the insulating film as a mask, removing the insulating film, depositing an oxide film on the resultant, and then forming an upper portion of the silicon substrate. Isotropic etching to form a BN layer to provide a method for manufacturing a semiconductor device, characterized in that consisting of.
본 발명은 상기 트랜치를 비등방성 플라즈마 식각으로 실리콘기판 표면으로부터 300 ~ 400Å 오버식각하여 형성한 후, BN 이온인 As 이온을 20~30°기울기로 경사 주입하여 트랜치 주변에 BN 정션을 형성하는 것을 특징으로 한다. According to the present invention, the trench is formed by anisotropic plasma etching over 300 to 400 Å from the surface of the silicon substrate, and then, as the BN ions are inclined at 20 to 30 °, the BN junction is formed around the trench. It is done.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명하고자 한다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 도 3d는 본 발명의 실시예에 따른 반도체소자의 제조방법을 설명하기 위해 순차적으로 나타낸 공정 단면도이다.3A through 3D are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
먼저, 도 3a에 도시된 바와 같이 p형 실리콘기판(10)에 필드산화막(30)을 형성하여 소자를 분리하는 소자분리영역과 소자를 형성하는 활성영역으로 정의한 후, n-웰(20)을 형성한다.First, as shown in FIG. 3A, the
그리고, 도 3b에 도시된 바와 같이 상기 실리콘기판(10) 상에 질화물을 900~1100Å, 바람직하게는 약 1000Å 정도 증착하여 절연막(40)을 형성하고 절연막(40) 상부에 감광막을 도포한 후 노광 및 현상공정을 진행하여 BN층 형성영역이 개방되도록 감광막 패턴(미도시함)을 형성한다.As shown in FIG. 3B, nitride is deposited on the
이어서, 상기 감광막 패턴(미도시함)을 마스크로 하여 절연막(40)을 비등방성 플라즈마 식각으로 실리콘기판(10)을 표면으로부터 300 ~ 400Å 오버식각하여 실리콘기판(10) 내에 깊이 300 ~ 400Å의 트랜치(50)를 형성한다.Subsequently, the
이때, 상기 트랜치(50)는 비등방성 플라즈마 식각에 의해 트랜치(50)의 하부가 날카롭게 형성된다.At this time, the
그 후, 도 3c에 도시된 바와 같이 상기 절연막(미도시함)을 이온주입 마스크로 BN 이온으로 As 이온을 노출된 실리콘기판 내에 20~30°기울기로 경사 주입하여 트랜치(50) 주변에 BN 정션(60)을 형성한 후, 이온주입 마스크로 이용한 절연막(미도시함)을 제거한다.
Thereafter, as shown in FIG. 3C, the insulating film (not shown) is inclinedly injected into the silicon substrate exposed to the BN ions using a ion implantation mask at an angle of 20 to 30 ° in the exposed silicon substrate to the BN junction around the
그리고, 도 3d에 도시된 바와 같이 상기 결과물 상에 블랭켓(blanket)으로 약 450~550Å 정도 산화막(미도시함)을 증착한 후, 실리콘기판(10) 상부까지 등방성 식각하여 산화막(미도시함) 상부가 라운딩지게 BN층(70)을 형성함으로써, 트랜치형 BN 구조를 형성한다.As shown in FIG. 3D, an oxide film (not shown) is deposited on the resultant with a blanket about 450 to 550 Å, and isotropically etched to the upper portion of the
그 결과, 상기 트랜치형 BN 구조는 기존의 옥시데이션 공정에 의해 형성되던 산화막의 버즈빅 형성을 방지하여 반도체소자의 특성 및 신뢰성을 향상시킬 수 있으며, 이온주입 후 확산공정에 의해 형성되던 BN 정션을 이온주입만으로 형성할 수 있어 공정을 단순화시킬 수 있다.
As a result, the trench type BN structure can improve the characteristics and reliability of the semiconductor device by preventing the formation of the oxide film formed by the conventional oxidation process, and the BN junction formed by the diffusion process after ion implantation. It can be formed only by ion implantation, which simplifies the process.
따라서, 상기한 바와 같이, 본 발명에 따른 반도체소자의 제조방법을 이용하게 되면, 실리콘기판에 비등방성 식각에 의해 트랜치를 형성하여 트랜치 주변에 경사 이온주입하여 BN 정션을 형성한 후, 트랜치 내에 산화막을 매립하여 BN층을 형성하는 것을 특징으로 하는 트랜치형 BN 구조를 형성함으로써 셀 영역을 평탄하게 형성시켜 소자의 동작 속도를 증가시킬 수 있을 뿐만 아니라 BN 정션의 안정화를 향상시켜 반도체소자의 특성 및 신뢰성을 개선하여 향상시키는 이점이 있다.Therefore, as described above, when the method of manufacturing a semiconductor device according to the present invention is used, a trench is formed on the silicon substrate by anisotropic etching to form a BN junction by inclining ion implantation around the trench, and then an oxide film is formed in the trench. By forming the trench type BN structure, which forms a BN layer by filling the gap, the cell region can be formed flat to increase the operation speed of the device, and improve the stability of the BN junction to improve the characteristics and reliability of the semiconductor device. There is an advantage to improve by improving.
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| KR19980085788A (en) * | 1997-05-30 | 1998-12-05 | 윤종용 | Trench element isolation formation method of semiconductor device |
| KR19990045444A (en) * | 1997-11-20 | 1999-06-25 | 가네꼬 히사시 | Nonvolatile Semiconductor Memory Device and Manufacturing Method Thereof |
| KR20020050363A (en) * | 2000-12-21 | 2002-06-27 | 박종섭 | Method of manufacturing a semiconductor device |
| KR20020055904A (en) * | 2000-12-29 | 2002-07-10 | 박종섭 | Method of manufacturing a semiconductor device |
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| KR19980085788A (en) * | 1997-05-30 | 1998-12-05 | 윤종용 | Trench element isolation formation method of semiconductor device |
| KR19990045444A (en) * | 1997-11-20 | 1999-06-25 | 가네꼬 히사시 | Nonvolatile Semiconductor Memory Device and Manufacturing Method Thereof |
| KR20020050363A (en) * | 2000-12-21 | 2002-06-27 | 박종섭 | Method of manufacturing a semiconductor device |
| KR20020055904A (en) * | 2000-12-29 | 2002-07-10 | 박종섭 | Method of manufacturing a semiconductor device |
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