JPH0964302A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the decrease of process margin which is to be caused by excessive etching of an oxide film at the time of forming a contact hole. SOLUTION: A first wiring part 8 of a transistor is covered with first nitride film pattern 30 and a nitride film side wall part 32. After a first oxide film is deposited, a first contact hole 15 is formed by etching. After a second doped polysilicon film is deposited, a storage electrode 18 is formed by etching, and further a capacitor insulating film 19 for forming a capacitor and a cell plate electrode 22 are formed. After a BPSG film 23 is deposited, a second contact hole 25 is formed by etching. After a fourth doped polysilicon film 26 and a tungsten silicide film 27 is deposited, a second wiring part 28 is formed by etching. Thereby the first wiring part 8 is protected from the etching at the time of forming the first contact hole 15, and process margin is improved, so that a capacitor can be simply formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a countermeasure for forming a contact hole.

[0002]

2. Description of the Related Art In recent years, as the density and integration of semiconductor integrated circuits have increased, it has become necessary to improve fine processing technology.
As such a conventional semiconductor device, a method of manufacturing a complementary MOS integrated circuit device will be described as an example with reference to process sectional views of FIGS. The complementary MOS integrated circuit device manufactured by this manufacturing method is a top-mounted type in which the wiring portion is above the storage electrode.

First, as a first manufacturing process, as shown in FIG. 19, for example, a selective oxide film 2 for separating a transistor formation region and other regions is formed on a P-type silicon semiconductor substrate 1, and then a gate is formed. An oxide film 3 is deposited, a 200 nm first doped polysilicon film 4 and a 300 nm first oxide film 5 are sequentially deposited thereon, and then a first photoresist pattern 6 is formed thereon. .

Next, as a second manufacturing process, as shown in FIG. 20, a portion of the first oxide film 5 not covered with the first photoresist pattern 6 is etched by anisotropic dry etching to form a first oxide film 5. An oxide film pattern 7 of No. 1 is formed.

Next, as a third manufacturing step, as shown in FIG. 21, after the first photoresist pattern 6 is removed, the first photoresist pattern 6 which is not covered with the first oxide film pattern 7 is removed.
A portion of the doped polysilicon film 4 is etched by anisotropic dry etching to form a first wiring portion 8.
Further, low-concentration source / drain regions 9 are formed by ion implantation of phosphorus.

Next, as a fourth manufacturing process, as shown in FIG. 22, a 250 nm second oxide film 10 is deposited as an interlayer insulating film.

Next, as a fifth manufacturing step, as shown in FIG. 23, the second oxide film 10 is etched by the entire surface oxide film etching to form an oxide film side wall portion 11, and thereafter, boron is further formed. A high concentration source / drain region 12 is formed by ion implantation.

Next, as a sixth manufacturing step, as shown in FIG. 24, after depositing a 150 nm third oxide film 13, a second photoresist pattern 14 is formed.

Next, as a seventh manufacturing step, as shown in FIG. 25, a portion of the third oxide film 13 which is not covered with the second photoresist pattern 14 is etched by oxide film dry etching to form a first oxide film. Contact hole 15
Then, the second photoresist pattern 14 is removed.

Next, as an eighth manufacturing step, as shown in FIG. 26, after depositing a 600 nm second doped polysilicon film 16, a third photoresist pattern 17 is formed.

Next, as a ninth manufacturing step, as shown in FIG. 27, a portion of the second doped polysilicon film 16 which is not covered with the third photoresist pattern 17 is etched by dry etching and accumulated. The electrode 18 is formed. Furthermore, 80 nm for forming a capacitor
After depositing the capacitive insulating film 19 of, a third doped polysilicon film 20 of 200 nm is deposited. After that, a fourth photoresist pattern 21 is further formed thereon.

Next, as a tenth manufacturing process, as shown in FIG. 28, a portion of the third doped polysilicon film 20 not covered with the fourth photoresist pattern 21 is etched by dry etching to form a cell. The plate electrode 22 is formed. After that, the fourth photoresist pattern 21 is removed, and a 700 nm BPSG film 23 is deposited thereon as an interlayer insulating film, and then a fifth photoresist pattern 24 is formed.

Next, as an eleventh manufacturing step, as shown in FIG. 29, the portion of the BPSG film 23 not covered with the fifth photoresist pattern 24 is etched by dry etching to form the second contact hole 25. Form. Then, the fifth photoresist pattern 24 is removed, and a 150 nm fourth doped polysilicon film 26 and a 150 nm tungsten silicide film 27 are sequentially deposited on the fifth photoresist pattern 24, and the fourth doped polysilicon film is deposited. A second wiring portion 28 made of the tungsten silicide film 27 and the tungsten silicide film 27 is formed.

[0014]

However, in the above-described conventional manufacturing method, the first wiring portion 8 is covered with the same oxide film as the third oxide film 13 which is the upper layer, and is formed. The opening size of the first contact hole 15 in the substrate is smaller than the opening size of the photoresist pattern 14 due to the oxide film side wall portion 11 on the side portion of the first wiring portion 8. If the third oxide film 13 is etched for a long time to form the contact hole 15, the oxide film pattern 7 and the oxide film side wall part 11 of the first wiring part 8 are also etched, and then formed. There is a possibility that the storage electrode and the wiring may be short-circuited, resulting in a small process margin.

The present invention has been made in view of the above circumstances, and an object thereof is to manufacture a semiconductor device in which a process margin at the time of forming a contact between a storage electrode and a substrate is improved and a capacitor can be easily formed. Is to provide a method.

[0016]

To achieve the above object, the present invention is characterized in that a nitride film having a smaller etching rate than an insulating film such as an oxide film is used as an insulating film around a contact hole. To do.

Specifically, the first solving means of the present invention is
First, after forming a transistor having a first wiring portion covered with a nitride film on a semiconductor substrate, an interlayer insulating film having an etching rate higher than that of the nitride film is deposited on the transistor, and the interlayer insulating film is etched. To form a first contact hole. Next, a conductive film is deposited on the interlayer insulating film after the etching, and the conductive material is embedded in the first contact hole. Next, the conductive film is etched to form an electrode. Next, an interlayer insulating film is deposited on the electrode and the interlayer insulating film is etched to form a second contact hole. Next, a conductive film is deposited on the interlayer insulating film after the etching, and the conductive material is embedded in the second contact hole. Finally, the method is characterized by including a manufacturing step of etching the conductive film to form a second wiring portion.

According to a second solution of the present invention, first, a transistor having a first wiring portion covered with an oxide film is formed on a semiconductor substrate, and then an interlayer having an etching rate higher than that of a nitride film is formed thereon. An insulating film is deposited and this interlayer insulating film is etched to form a first contact hole.
Next, a conductive film is deposited on the etched interlayer insulating film, and the conductive material is embedded in the second contact hole. Next, the conductive film is etched to form a second wiring portion. Next, an interlayer insulating film having a nitride film as an upper layer is deposited on the second wiring portion, and the interlayer insulating film is etched to form a second contact hole. Next, a conductive film is deposited on the interlayer insulating film after the etching, and the conductive material is embedded in the second contact hole. Finally, a manufacturing step of etching the conductive film to form an electrode is provided.

With the above structure, in the first solution of the present invention, since the first wiring portion forming the transistor is covered with the nitride film, the opening size of the first contact hole on the substrate side is reduced. Although it is smaller than the opening size on the electrode side above it, since the etching rate of the nitride film is smaller than the etching rate of the interlayer insulating film thereabove, this interlayer insulating film is etched to form the first contact hole. At the time of forming, the nitride film covering the first wiring portion is hardly etched even if the etching time is long, the process margin is improved, and the formation of the capacitor is simplified.

In the second solving means of the present invention, since the etching rate of the nitride film is smaller than the etching rate of the interlayer insulating film thereunder, the second wiring portion is deeper below the electrode. When the second contact hole is formed, the nitride film serves as a mask, and even if the etching time is long, the upper portion of the lower interlayer insulating film is not overetched and the second contact hole having a predetermined hole diameter is formed. Contact holes are obtained, thus improving the process margin and simplifying the formation of capacitors.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIGS. 1 to 11 are process cross-sectional views showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention. Specifically, the wiring portion is located above the storage electrode. The present invention relates to a method of manufacturing an upper type complementary MOS integrated circuit device. 1 to 11, the same parts as those in FIGS. 19 to 29 showing the conventional example are designated by the same reference numerals.

First, as a first manufacturing process, as shown in FIG. 1, for example, after forming a selective oxide film 2 for separating a transistor forming region and other regions on a P-type silicon semiconductor substrate 1, a gate is formed. An oxide film 3 is deposited, and a 200 nm first doped polysilicon film (a polysilicon film may be doped with phosphorus) 4 and 300
nm first nitride film 29 is sequentially deposited. Further, a first photoresist pattern 6 is formed thereon.

Next, as a second manufacturing process, as shown in FIG. 2, the portion of the nitride film 29 not covered with the first photoresist pattern 6 is etched by anisotropic dry etching to form the first nitride film. The film pattern 30 is formed.

Next, as a third manufacturing process, as shown in FIG. 3, after removing the first photoresist pattern 6 as in the conventional example, it is not covered with the first nitride film pattern 30. A portion of the first doped polysilicon film 4 is etched by anisotropic dry etching to form a first wiring portion 8. Further, low-concentration source / drain regions 9 are formed by ion implantation of phosphorus.

Next, as a fourth manufacturing process, as shown in FIG. 4, a second nitride film 31 of 250 nm is deposited as an interlayer insulating film.

Next, as a fifth manufacturing step, as shown in FIG. 5, the second nitride film 31 portion is entirely etched by nitride film etching to form a nitride film side wall portion 32,
Further, a high concentration source / drain region 12 is formed by ion implantation of boron.

Next, as a sixth manufacturing process, as shown in FIG. 6, as in the conventional example, the first oxide film 13 (third oxidation of the conventional example) having a larger etching rate than the nitride film and having a thickness of 150 nm is used. A second photoresist pattern 14 is formed after the deposition of the same reference numeral as the film (see FIG. 24).

Next, as a seventh manufacturing step, as shown in FIG. 7, a portion of the first oxide film 13 which is not covered with the second photoresist pattern 14 is etched by oxide film dry etching to form a first oxide film 13. After the contact hole 15 is formed, the second photoresist pattern 14 is removed.

At this time, since there is the nitride film side wall portion 32, the opening size of the first contact hole 15 on the substrate side is smaller than the opening size of the second photoresist pattern 14, Since the etching rate is smaller than the etching rate of the oxide film, the nitride film pattern 30 and the nitride film sidewall portion 32 are hardly etched even if the etching time is lengthened, and the process margin at the time of forming the first contact hole 15 is improved. Further, the capacitor can be easily formed in the tenth manufacturing process described later.

Next, as an eighth manufacturing step, as shown in FIG. 8, a 600 nm second doped polysilicon film (a polysilicon film doped with phosphorus) is formed as a conductive film as in the conventional example. After that, a third photoresist pattern 17 is formed.

Next, as a ninth manufacturing step, as shown in FIG. 9, the second doped polysilicon film 16 portion not covered with the third photoresist pattern 17 is dried as in the conventional example. The storage electrode 18 is formed by etching. Furthermore, after depositing a capacitive insulating film 19 of 80 nm for forming a capacitor, 200
A third doped polysilicon film (which may be a polysilicon film doped with phosphorus) 20 having a thickness of 20 nm is deposited. After that, a fourth photoresist pattern 21 is further formed thereon.

Next, as a tenth manufacturing process, as shown in FIG. 10, the third doped polysilicon film 20 portion which is not covered with the fourth photoresist pattern 21 is dried as in the conventional example. The cell plate electrode 22 is formed by etching. After that, the fourth photoresist pattern 21 is further removed, and a 700 nm BPSG film 23 is further deposited thereon as an interlayer insulating film, and then a fifth photoresist pattern 24 is formed.

Finally, as an eleventh manufacturing process, FIG.
As shown in FIG. 5, similarly to the conventional example, the BPSG film 23 portion not covered with the fifth photoresist pattern 24 is etched by dry etching to form the second contact hole 25. Further, the fifth photoresist pattern 24 is removed, and a 150 nm fourth doped polysilicon film (a polysilicon film may be doped with phosphorus) 26 and 15 is formed thereon as a conductive film.
A tungsten silicide film 27 having a thickness of 0 nm is sequentially deposited, and the second contact hole 25 is filled with doped polysilicon as its conductive material. Finally, the fourth doped polysilicon film 26 and the tungsten silicide film 27 are etched to etch the fourth doped polysilicon film 26 and the tungsten silicide film 27.
And the second wiring part 28 is formed.

(Second Embodiment) FIGS. 12 to 18 are process cross-sectional views showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention. Specifically, the wiring portion is located below the storage electrode. The present invention relates to a method of manufacturing an underlay type complementary MOS integrated circuit device. In addition, in FIGS.
The same parts as those in FIGS. 19 to 29 showing the conventional example are designated by the same reference numerals.

First, as a first manufacturing process, as shown in FIG. 12, similar to the conventional example, for example, a selective oxide film 2 for separating a transistor formation region and other regions is formed on a P-type silicon semiconductor substrate 1. After the formation of the gate oxide film 3,
The oxide film pattern 7 and the first wiring portion 8 are formed. Further, low-concentration source / drain regions 9 are formed by ion implantation of phosphorus. Note that, in the second embodiment, the process diagrams corresponding to FIGS. 19 and 20 of the conventional example as the former stage process of this manufacturing process are omitted.

Next, as a second manufacturing process, as shown in FIG. 13, an oxide film side wall 11 is formed as in the conventional example, and further, a high concentration source / drain region 12 is formed by boron ion implantation. To form. In addition, in the second embodiment, a process diagram corresponding to FIG. 22 of the conventional example as a former stage process of this manufacturing process is omitted.

Next, as a third manufacturing step, as shown in FIG. 14, after depositing a 500 nm first BPSG film 33 as an interlayer insulating film having an etching rate higher than that of the nitride film, a second photoresist pattern is formed. 34 is formed.
Further, the portion of the first BPSG film 33 not covered with the second photoresist pattern 34 is etched by dry etching to form the first contact hole 35.

Next, as a fourth manufacturing step, as shown in FIG. 15, after removing the second photoresist pattern 34, a 150 nm second doped polysilicon film (polysilicon film is formed) is formed as a conductive film. (Phosphorus doped) 26 and 150 nm tungsten silicide film 27
And the doped polysilicon as the conductive material is embedded in the first contact hole 35. After that, the second doped polysilicon film 2 is formed.
6 and the tungsten silicide film 27 are etched to form a second wiring portion 28 composed of the second doped polysilicon film 26 and the tungsten silicide film 27. Further, a 600 nm second BPSG film 36 and a 150 nm first nitride film 37 are sequentially deposited as an interlayer insulating film, and then a third photoresist pattern 38 is formed.

Next, as a fifth manufacturing step, as shown in FIG. 16, a portion of the first nitride film 37 not covered with the third photoresist pattern 38 is etched by dry etching to form a nitride film pattern 39. After forming, the third
Then, the photoresist pattern 38 is removed. Further, the first and second B not covered with the nitride film pattern 39 are formed.
The PSG films 33 and 36 are etched by dry etching to form a second contact hole 40.

At this time, the etching rate of the nitride film is BP.
Since it is smaller than the etching rate of the SG film, the second
The storage electrode 1 in which the wiring portion 28 is formed in the seventh manufacturing process
When the second contact hole 40 which is deeper than 8 is formed, the first nitride film 37 serves as a mask, and the second BPS is formed even if the etching time is long.
Excessive etching of the upper portion of the G film 36 can be prevented, and the second contact hole 40 can be formed to have a predetermined hole diameter, whereby the process margin can be improved and the capacitor can be easily formed. Can be formed.

Next, as a sixth manufacturing process, as shown in FIG. 17, a 600 nm third doped polysilicon film (a polysilicon film may be doped with phosphorus) 41 is deposited as a conductive film. At the same time, doped polysilicon is buried in the second contact hole 40, and a fourth photoresist pattern 42 is formed thereon.

Finally, as a seventh manufacturing step, as shown in FIG. 18, the portion of the third doped polysilicon film 41 which is not covered with the fourth photoresist pattern 42 is etched by dry etching and accumulated. The electrode 18 is formed. Further, after depositing an 80 nm capacitive insulating film 19 for forming a capacitor on the storage electrode 18, a 200 nm doped polysilicon film (a polysilicon film may be doped with phosphorus) is deposited, Further, a photoresist pattern is formed thereon, and the doped polysilicon film portion not covered with this photoresist pattern is etched by dry etching to form the cell plate electrode 22.

In each of the above embodiments, the method of manufacturing the complementary MOS integrated circuit device using the P-type silicon semiconductor substrate 1 as the semiconductor substrate is shown, but the same applies to the case of using the N-type silicon semiconductor substrate. The effect of can be obtained.

[0045]

As described above, according to the present invention of claim 1, since the wiring portion of the transistor is covered with the nitride film having an etching rate smaller than that of the interlayer insulating film on the transistor, the interlayer insulating film is covered. When the contact hole is formed by etching, the wiring portion can be protected by the nitride film to improve the process margin, and the capacitor can be easily formed.

According to the second aspect of the present invention, when a deep contact hole is formed by providing a nitride film having an etching rate smaller than that on the interlayer insulating film forming the contact hole, an upper portion of the contact hole is formed. However, it is possible to improve the process margin by eliminating a large diameter due to excessive etching, and it is possible to easily form a capacitor.

[Brief description of drawings]

FIG. 1 is a process cross-sectional view showing a first manufacturing process in a method of manufacturing a complementary MOS integrated circuit device according to a first embodiment.

FIG. 2 is a process sectional view showing a second manufacturing process in the method of manufacturing the complementary MOS integrated circuit device according to the first embodiment.

FIG. 3 is a process sectional view showing a third manufacturing process in the method for manufacturing the complementary MOS integrated circuit device according to the first embodiment.

FIG. 4 is a process sectional view showing a fourth manufacturing step in the method for manufacturing the complementary MOS integrated circuit device according to the first example.

FIG. 5 is a process sectional view showing a fifth manufacturing step in the method of manufacturing the complementary MOS integrated circuit device according to the first example.

FIG. 6 is a process sectional view showing a sixth manufacturing step in the method for manufacturing the complementary MOS integrated circuit device according to the first example.

FIG. 7 is a process sectional view showing a seventh manufacturing step in the method for manufacturing the complementary MOS integrated circuit device according to the first example.

FIG. 8 is a process sectional view showing an eighth manufacturing process in the method of manufacturing the complementary MOS integrated circuit device according to the first example.

FIG. 9 is a process sectional view showing a ninth manufacturing process in the method for manufacturing the complementary MOS integrated circuit device according to the first example.

FIG. 10 is a process sectional view showing a tenth manufacturing step in the method of manufacturing the complementary MOS integrated circuit device according to the first example.

FIG. 11 is a process sectional view showing an eleventh manufacturing process in the method of manufacturing the complementary MOS integrated circuit device according to the first example.

FIG. 12 is a process sectional view showing a first manufacturing process in the method for manufacturing the complementary MOS integrated circuit device according to the second embodiment.

FIG. 13 is a process sectional view showing a second manufacturing process in the method for manufacturing the complementary MOS integrated circuit device according to the second embodiment.

FIG. 14 is a process sectional view showing a third manufacturing process in the method for manufacturing the complementary MOS integrated circuit device according to the second embodiment.

FIG. 15 is a process sectional view showing a fourth manufacturing process in the method for manufacturing the complementary MOS integrated circuit device according to the second example.

FIG. 16 is a process sectional view showing a fifth manufacturing process in the method for manufacturing the complementary MOS integrated circuit device according to the second example.

FIG. 17 is a process sectional view showing a sixth manufacturing step in the method for manufacturing the complementary MOS integrated circuit device according to the second example.

FIG. 18 is a process sectional view showing a seventh manufacturing step in the method for manufacturing the complementary MOS integrated circuit device according to the second example.

FIG. 19 is a process cross-sectional view showing a first manufacturing process in a method for manufacturing a complementary MOS integrated circuit device according to a conventional example.

FIG. 20 is a process sectional view showing a second manufacturing process in the method for manufacturing the complementary MOS integrated circuit device according to the conventional example.

FIG. 21 is a process sectional view showing a third manufacturing process in the method for manufacturing the complementary MOS integrated circuit device according to the conventional example.

FIG. 22 is a process sectional view showing a fourth manufacturing process in a method for manufacturing a complementary MOS integrated circuit device according to a conventional example.

FIG. 23 is a process sectional view showing a fifth manufacturing process in a method for manufacturing a complementary MOS integrated circuit device according to a conventional example.

FIG. 24 is a process sectional view showing a sixth manufacturing process in a method for manufacturing a complementary MOS integrated circuit device according to a conventional example.

FIG. 25 is a process sectional view showing a seventh manufacturing process in a method for manufacturing a complementary MOS integrated circuit device according to a conventional example.

FIG. 26 is a process sectional view showing an eighth manufacturing step in the method for manufacturing the complementary MOS integrated circuit device according to the conventional example.

FIG. 27 is a process sectional view showing a ninth manufacturing process in a method for manufacturing a complementary MOS integrated circuit device according to a conventional example.

FIG. 28 is a process sectional view showing a tenth manufacturing process in a method for manufacturing a complementary MOS integrated circuit device according to a conventional example.

FIG. 29 is a process sectional view showing an eleventh manufacturing process in a method for manufacturing a complementary MOS integrated circuit device according to a conventional example.

[Explanation of symbols]

 1 P-type semiconductor substrate 7 Oxide film pattern 8 First wiring part 11 Oxide film side wall part 13 Oxide film 15, 25, 35, 40 Contact hole 16, 26, 41 Doped polysilicon film 18 Storage electrode 23, 33, 36 BPSG film 27 Tungsten silicide film 28 Second wiring part 30 Nitride film pattern 32 Nitride film side wall part 37 Nitride film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/78

Claims (2)

[Claims] 1. After forming a transistor having a first wiring portion covered with a nitride film on a semiconductor substrate, an interlayer insulating film having an etching rate higher than that of the nitride film is deposited on the transistor, and the interlayer insulating film is deposited. A manufacturing step of etching the film to form a first contact hole; a manufacturing step of depositing a conductive film on the insulating film after the etching and filling the conductive material in the first contact hole; A manufacturing process of etching the film to form an electrode, a manufacturing process of depositing an interlayer insulating film on the electrode and etching the interlayer insulating film to form a second contact hole, and an interlayer after the etching. A manufacturing process of depositing a conductive film on the insulating film and filling the conductive material in the second contact hole, and etching the conductive film to form a second layer. The method of manufacturing a semiconductor device characterized by comprising a manufacturing process for forming a section. 2. After forming a transistor having a first wiring portion covered with an oxide film on a semiconductor substrate, an interlayer insulating film having an etching rate higher than that of a nitride film is deposited on the transistor, and the interlayer insulating film is formed. A step of etching to form a first contact hole, a step of depositing a conductive film on the interlayer insulating film after the etching, and a step of filling the conductive material in the second contact hole, A manufacturing process in which the film is etched to form a second wiring part, and an interlayer insulating film having a nitride film as an upper layer is deposited on the second wiring part, and the interlayer insulating film is etched to form a second wiring part. A manufacturing process of forming a contact hole, and a manufacturing process of depositing a conductive film on the interlayer insulating film after the etching and burying the conductive material in the second contact hole. The method of manufacturing a semiconductor device characterized by comprising a manufacturing step of forming an electrode by etching the conductive film.