TW200408053A - Method of forming a metal line in a semiconductor device - Google Patents
Method of forming a metal line in a semiconductor device Download PDFInfo
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- TW200408053A TW200408053A TW091133014A TW91133014A TW200408053A TW 200408053 A TW200408053 A TW 200408053A TW 091133014 A TW091133014 A TW 091133014A TW 91133014 A TW91133014 A TW 91133014A TW 200408053 A TW200408053 A TW 200408053A
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- Prior art keywords
- titanium
- film
- contact hole
- chamber
- power source
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- 238000000034 method Methods 0.000 title claims abstract description 82
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 65
- 239000002184 metal Substances 0.000 title claims abstract description 65
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 230000004888 barrier function Effects 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 230000008021 deposition Effects 0.000 claims abstract description 6
- 239000010936 titanium Substances 0.000 claims description 68
- 229910052719 titanium Inorganic materials 0.000 claims description 67
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 65
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 52
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 22
- 150000004767 nitrides Chemical class 0.000 claims description 11
- 229910052757 nitrogen Inorganic materials 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 4
- 230000008859 change Effects 0.000 claims description 3
- 150000003608 titanium Chemical class 0.000 claims description 2
- 238000000151 deposition Methods 0.000 abstract description 16
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052721 tungsten Inorganic materials 0.000 abstract description 12
- 239000010937 tungsten Substances 0.000 abstract description 12
- 150000002500 ions Chemical class 0.000 abstract description 8
- -1 fluorine ions Chemical class 0.000 abstract description 6
- 229910052731 fluorine Inorganic materials 0.000 abstract description 5
- 239000011737 fluorine Substances 0.000 abstract description 5
- 230000035515 penetration Effects 0.000 abstract description 3
- 230000008569 process Effects 0.000 abstract description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 235000012431 wafers Nutrition 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005121 nitriding Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- 241000220317 Rosa Species 0.000 description 1
- 229910004014 SiF4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910008479 TiSi2 Inorganic materials 0.000 description 1
- LCKIEQZJEYYRIY-UHFFFAOYSA-N Titanium ion Chemical compound [Ti+4] LCKIEQZJEYYRIY-UHFFFAOYSA-N 0.000 description 1
- 101100107923 Vitis labrusca AMAT gene Proteins 0.000 description 1
- 229910052769 Ytterbium Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 description 1
- WYEMLYFITZORAB-UHFFFAOYSA-N boscalid Chemical compound C1=CC(Cl)=CC=C1C1=CC=CC=C1NC(=O)C1=CC=CN=C1Cl WYEMLYFITZORAB-UHFFFAOYSA-N 0.000 description 1
- 238000009933 burial Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000035622 drinking Effects 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- NMJKIRUDPFBRHW-UHFFFAOYSA-N titanium Chemical compound [Ti].[Ti] NMJKIRUDPFBRHW-UHFFFAOYSA-N 0.000 description 1
- NAWDYIZEMPQZHO-UHFFFAOYSA-N ytterbium Chemical compound [Yb] NAWDYIZEMPQZHO-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/04—Coating on selected surface areas, e.g. using masks
- C23C16/045—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28568—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising transition metals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Crystallography & Structural Chemistry (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Description
200408053 ⑴ 玫、發明說明 實施方式及圖式簡單說明) (發明說明應敘明:發明所屬之技術領域、先前技術、内容、 發明背景 技術領城_ ·· 本發明一般與在半導體裝置中形成金屬線之方法相 關,且更特定地,與一種使用離子金屬電漿(IMP)方法形成 障礙金屬層之方法相關。 先前技藝: 最近,在使用於在半導體裝置中訊號轉移及功率應用之 金屬線中,在該等線之間的線寬度及距離因為整合之增加 程度而持續地窄化。隨著該趨勢,已經嘗試形成金屬線的 許多方法。金屬線之材料通常包括銘(A1 )、銅(c u)以及該等 之合金層。金屬線之材料埋至接觸洞,經由其一給定之接 合被暴露以形成具有所需厚度及寬度的金屬線。進一步 地,為了改進金屬線材料之缺陷的接觸洞埋葬特性,鶴(w) 插頭在接觸洞中形成且之後該金屬線在該插頭上形成。 然而,在該情況下,因為鋁金屬層或鎢插頭和半導體基 材的碎(Si)在接觸洞之底部反應,所以發生接合刺穿的現 象。結果,該接合刺穿導致降低半導體裝置之電氣特性及 可靠性。所以,為了防止接合刺穿現象,於是形成一内層 絕緣膜(ILD)。並且,為了防止半導體基材之梦(Si)離子在被 嫣層所埋葬之接觸洞的内表面上的擴散’形成一障礙金屬 (B/M)層。該障礙金屬層具有一結構,在其上堆疊鈦(Ti)和 氮化鈦(TiN)膜。 形成具有鈦/氮化鈦膜之堆疊結構之障礙金屬層的方法 包括傳統鈥/氮化鈦方法、平行鈦/傳統氮化鈦方法、IMp鈦 200408053 (2) 發明說明續頁 /化學氣相沉積(CVD)氮化鈦方法、IMP鈦/IMP氮化鈦方法(此 時’不施加AC偏壓電源)或是IMp鈦/平行氮化鈦方法。 圖1顯示當使用傳統鈦/氮化鈦方法和平行鈦/傳統氮化鈦 方法形成障礙金屬層時可獲得的障礙金屬層的剖面圖。 現在參考圖1 ’在使用傳統鈦/氮化鈦方法的情況下,一 内層絕緣膜12在半導體基材10上形成,該基材包括一給定 的記憶體單元和具有閘極和接合區域的電晶體。之後執行 微影和蝕刻方法以形成一接觸洞14 ,經由該楝該半導體基 材10的給定部份被打開。接著,鈦膜l6a和氮化鈦膜藉由 傳統方法,藉由該方法鈦和氮化鈦目標使用氬(Ar)氣體賤 擊’而隨後地在包括接觸洞丨4之整個結構上沉積,因此形 成一障礙金屬層16。 在另一方面,在使用平行鈦/傳統氮化鈦之方法的情況 下’接觸洞14在半導體基材1 〇中形成。接著,鈥使用氣氣 體而濺擊。此時,鈦膜16a使用平行方法形成,藉由該方法 在鈦微粒中僅具有筆直性的粒子被氬氣體所濺擊。之後, 該氮化鈥膜16b藉由傳統方法在鈦膜16a上沉積,因此形成該 障礙金屬層16。 如上所述,在使用傳統鈦/氮化鈦方法和平行鈦/傳統氮化 鈦方法之情況下,該障礙金屬層16在接觸洞14之底部的邊 緣部份(A1)不能具有鈦膜16a之足夠的階梯涵蓋率,因為在 内層絕緣膜12中形成之接觸洞14的尺寸因為半導體裝置整 合之增加程度而減少。結果,有接觸組抗被增加而產生在 半導體裝置中瑕疵的問題。 200408053 (3) 發明說明續頁 進一步地,甚至在氮化鈥膜16b的情況下,足夠階梯涵蓋 率特性不能在接觸洞14的底部之邊緣部份(A1)獲得。因為當 鎢層稍後埋葬時,在接觸洞14之内表面上形成之氮化欽膜 側邊的頂端部分的突出現象,一關鍵洞在鎢層内產生 (未顯示)$結果,存在裝置之電氣特性和可靠性被降低的 問題。 所以,在傳統鈦/氮化鈦方法和平行鈦/傳統氮化鈦方 π ’當鶏沉積時,鈥/氮化鈥膜之階梯涵蓋率在接觸洞之底 部之邊緣部份被弱化,氟(F)與半導體基材的矽(Si)離子反 應。所以,有鎢穿入半導體基材,像圖3之部份(A3)之問題。 進一步地,歸因於增加接觸組抗,因為F離子穿入在接觸洞 底部之TiSi2的底部,因此形成一非精細層,存在裝置中的 失敗問題。 圖2顯示當使用IMP鈦/CVD氮化鈦方法及IMP鈦/IMP氮化 致方法形成障礙金屬層時可獲得之障礙金屬層的剖面圖。 現在參考圖2,在使用IMP鈦/CVD氮化鈦方法之情況下, 内層絕緣膜22在半導體基材20上形成。之後執行微影和蝕 刻方法以形成接觸洞24,經由其半導體基材20之給定部份 被打開。接著,藉由IMP方法形成鈦膜26a而氮化鈦膜26b也 藉由使用TDEAT+NH3來源之CVD方法在該鈦膜26a上形成。之 後,在内層絕緣膜22中形成之接觸洞24的底部部分藉由電 漿處理而晶體化。結果,可改進分別膜之階梯涵蓋率。 在另一方面,該IMP鈦/IMP氮化鈦係為一種方法,藉由其 鈦膜26a和氮化鈦膜26b藉由IMP方法,在半導體基材20上隨 200408053 (4) · •發明碍明續頁 後地沉積,在該基材中形成接觸洞24·,因此形成障凝金屬 層26 〇 如上所述,在使用IMP鈦/CVD氮化鈦方法及imp鈦/IMP氮 化鈦方法之情況下,接觸洞之側牆保持完整如非晶矽相 位。因此,在隨後退火方法上,在接觸洞之底部之部份(A2) 的氮化鈦膜26b不能夠連續地形成。因為此,在鎢層之隨後 沉積方法上,鶴容易地穿入接觸洞之底部之邊緣部份,如 圖4中之(A4)。因為氟離子和該半導體基材之矽離子反應, 因此介電膜在邊緣部份形成。結果’有接觸組抗增加導致 裝置之失敗的問題。此外,因為在接觸洞之側牆的階梯涵 蓋率非常弱,在鎢層之沉積上,氟離子之F-基礎與半導體 基材的梦離子反應,因此形成SiF4。結果,此阻礙埋葬鎢層 之隨後方法。 如上所述,當利用先前技藝傳統鈦/氮化鈦方法、平行鈦 /傳統氮化鈦方法、IMP鈥/CVD氮化鈥方法和IMP鈥/IMP氮化 鈥方法時發生的裝置失敗將參考圖5A和圖5B而描述。 圖5A和圖5B顯示用以解釋因為根據顯示在圖3和4發生之 降低的電導(1/R)特性,裝置之功能失敗的特徵。 如可從圖5A看到,在因為氟離子之穿入產生之失敗單元 (FC)之情況下,取決於單元電壓(Vpx),在單元汲極電流中 幾乎沒有變化。在另一方面中,在氟離子沒有穿入之正常 單元(NC)的情況下,單元汲極電流在給定門檻電壓突然地 改變。同時,假如FC由因為氟離子穿入在接觸洞底部墻加 的接觸組抗而產生,施加至鄰近單元閘極電極的電流量的 200408053 (5) 變異當單元閘極電整急速變動時減少,因此羞 最大梯度(GM)單元。 進一步地,如可從圖5B看到,在NC之情況下 保持在常數範圍(4.5伏到5伏)。在另一方面, 下,門檻電壓增加至5.5伏到9.9伏。 發明内容 設計本發明以解決上述問題而本發明之目的 導體裝置中形成金屬線的方法,藉由該方法在1 形成鈦/氮化鈦之障礙金屬層的方法上施加增 電源以增加在接觸洞底部之邊緣部份的鈥/氮 厚度,使得可在沉積鎢層之隨後方法上防止氣 導體基材》 為了完成上述.目的’根據本發明,一種在半 形成金屬線的方法’其特徵為其包括下列步驟 i ^以層絕㈣’其中形成給定之結構 層絕緣膜以形成接觸洞;在接觸洞之内表面上 屬層,其中障礙金屬層之剖面藉由施加AC偏 疋以及形成接觸插頭,藉由其該接觸洞被埋 整個結構上形成金屬線。 貫施方式 本發明將藉由參考隨附圖式之一較佳具體實 地描述。 圖6A至圖6C係為半導體裝置之剖面檢視圖, 製造根據本發明之較佳具體實施例的半導體裝 發明說明續頁 .生2-位元列 ’門檻電壓 在FC的情況 係提供在半 吏用IMP方法 加之AC偏壓 化鈦之沉積 離子穿入半 導體裝置中 :在半導體 ;蝕刻該内 形成障礙金 壓電源而決 葬且之後在 施例而詳細 其用以描述 置的方法。 -10- 200408053 ⑹ 發明說明續頁 現在參考圖6A,内層絕緣膜102在半導體基材1〇〇上形成, 其中形成用以形成記憶體單元和電晶體的閘極電極和接合 區域(未顯示)。之後實施化學機械研磨(CMP)方法以平面化 内層絕緣膜102。 接著,在光阻在整個結構上覆蓋之後,實施使用遮罩之 暴露方法以形成光阻圖案(未顯示),經由其半導體基材100 之給定部份被打開。之後,實施使用光阻圖案如蝕刻遮罩 之蝕刻方法以形成接觸洞104,經由該洞打開半導體基材100 之給定部份。 藉由參考圖6B,保留在接觸洞104之内表面上的微粒藉由 一給定的潔淨方法移除以改進在接觸洞104之内表面上的 介面特性。接著,為了防止接合刺穿在半導體基材100之介 面和金屬膜發生,藉由其因為在其之間的反應接觸洞104被 埋葬,鈦膜106a和氮化鈦膜l〇6b在接觸洞1〇4之内表面和内層 絕緣膜102上隨後地沉積,因此形成障礙金屬層106。 在此時,障礙金屬層106可藉由在單一室中沉積鈦膜l〇6a 和氮化鈥膜l〇6b或藉由獨立地沉積該等膜在兩室中而形 成。一般地,沉積設備可包括由AMAT公司所製造的“Endura 系統”,藉由該設備1%1>鈦/IMP氮化鈦方法微調可容易地使 用。 在使用單一室沉積鈦膜l〇6a和氮化鈦膜i〇6b之情況下,首 先藉由施加1.5至3.0千瓦之DC電源、1.5至3.0千瓦之RF電源和 200至500瓦之AC偏壓電源,在室壓保持在10至50毫陶爾的狀 態中沉積鈦膜l〇6a。接著’在室内之情況保持和鈦膜106a之 200408053 ⑺ 發明說明續頁 沉積狀況幾乎相同的狀態中,藉由注入氮氣在鈦膜1(>6a上沉 積氮化鈥膜106b。在沉積氮化鈦膜1〇6b之方法期間,室壓藉 由氮氣注入該室中保持在20至100毫陶爾。在此時,為了鈦 膜106a之沉積目標係以接觸洞1〇4之底部為基礎為在50至100 埃的厚度’該飲膜106a以半導體基材100為基礎沉積1〇〇至500 埃之厚度。 在另一方面,在使用兩室沉積鈦膜l〇6a和氮化鈦膜i〇6b之 情沉下,在第一室保持10至50毫陶爾之壓力之狀態下,首 籲 先藉由施加1.5至3.0千瓦之dc電源、1.5至3.0千瓦之RF電源以 及200至500瓦之AC偏壓電壓沉積鈦膜l〇6a。接著,以在第一 室相同情況但是額外地該半導體基材100移到氮氣被注入 ‘ 之該第二室,該氮化鈦膜l〇6b在鈦膜106a上沉積。 私 在此時,第二室之壓力藉由氮氣保持在20至100毫陶爾。 進一步地,為了鈦膜l〇6a之沉積目標係以接觸洞104之底部 為基礎在50至100埃的厚度,該鈦膜l〇6a以半導體基材100為 基礎沉積100至500埃之厚度。 φ 同時,在鈦膜106a和氮化鈦膜i〇6b在單一室中沉積之情況 下,最後在室中沉積之膜包括鈦膜/氮化鈦膜和鈦膜。在此 時,假如該沉積方法在晶圓前置方法上在氮氣中完成,當 新晶圓引進至該室以形成障礙金屬層時,該氮化鈦膜在隨 後晶圓(即是,新晶圓)而不是鈦膜上首先地沉積。此導致 降低電氣特性。該原因係為沉積方法係在氮氣在氮化鈦膜 沉積之後被排除的狀態下完成。此時,在氮化鈦膜上沉積 之該鈦膜藉由使用氮氣之隨後退火方法改變至氮化鈦膜。 -12- 200408053 ⑻ 發明說明續頁 現在參考圖6C,實施一給定之退火方法以退火該障礙金 屬層106。接著,在接觸洞1〇4和障礙金屬層1〇6上沉積鶴層 108使得該接觸洞1〇4被埋葬。雖然在圖式中未顯示,該鎢層 108被蚀回使得在内層絕緣膜1〇2上形成之氮化鈦膜1〇6b暴 露。在銘金屬膜在氮化鈥膜l〇6b和鎢層1〇8上沉積之狀態 下,圖案化該鋁金屬膜和障礙金屬層1〇6以形成金屬線。 如上所述,使用IMP方法實施用以形成障礙金屬層1〇6之 沉積欽膜106a和氮化鈦膜l〇6b之方法。在此時,為了獲得例 如圖6B中的“B1”的剖面,需要在沉積方法上施加給定量上 之AC偏壓電源。施加增加之AC電壓電源之原因係藉由加強 障礙金屬層106之特性和厚厚地形成在接觸洞1〇4底部之邊 緣部份形成之氮化鈥膜l〇6b而克服傳統問題β 因此,在IMP鈇/IMP氮化歛方法中之ac偏壓電源係為決定 障礙金屬層剖面之最重要因素。 取決AC偏壓電源量在障礙金屬層的剖面中之變化現在將 參考圖7A至圖7C詳細地描述。 現在參考圖7A’顯示當施加0至50瓦之AC偏壓電源時障礙 金屬之剖面。從該圖式,可看見在接觸洞104底部之邊緣部 份“B2”具有與藉由使用普通物理氣相沉積(PVD)方法之金 屬沉積方法所沉積的障礙金屬層106的相同剖面。因此,發 生在傳統障礙金屬層中之相同問題。 藉由參考圖7B,顯示當施加100至150瓦之AC偏壓電源,障 礙金屬層之剖面。從該圖式,可看見在接觸洞104之底部中 央突出之部分“B2”如圖7A所顯示藉由施加1〇〇瓦至150瓦之 200408053 (9) 發明說明續頁 增加的AC偏壓電源被製造為像邊緣部份“B3’’之常數尺寸。
現在參考圖7C,顯示當施加200至500瓦之八(:偏壓電壓"時障 礙金屬層之剖面。不像圖7B中之剖面“B3” ’可看見在接觸 洞104之底部的邊緣部份“B4”具有凹剖面。該原因係為因為 障礙金屬層106在邊緣部份“B4,,和接觸洞104之底部之側邊 部分厚厚地形成,其歸因於一先前沉積層被具有由於高AC 偏壓電源之高能量之鈦離子重新濺擊,同時其與在接觸洞 底部之鈦膜或氮化鈦膜碰撞。 如上所述,根據本發明,當使用IMP方法形成鈦/氮化鈦 之障礙金屬層時,施加增加的AC偏壓電源以增加在接觸洞 之底部之邊緣部份的鈦/氮化鈦的沉積厚度。所以,本發明 具有一優點在於其在沉積隨後鎢層之方法上可防止氟(F) 離子之穿入至半導體基材。 進一步地,在使用IMP方法形成障礙金屬層之方法上適當 地控制AC偏壓電源。所以,本發明具有一優點在於其可防
土裝置之失敗,改進裝置之特性且增加良率,因為在沉積 隨後鎮層之方法上可防止氟(F)離子穿入至半導體基材。 本發明已經參考特別具體實施例一起與特別應用而描 述。熱悉此议蟄的人士和接觸到本發明之教誨將承認在其 範圍内之額外修改和應用^ 所又|增附申請專利範圍的企圖係為涵蓋在本發明 圍内《任何及王部廷樣之應用、修改、和具體實施例。 圖式簡單說明 本發明之前述勸1 ^ & 硯·..·占和,、他特點將一起與隨附圖式,在
-14· 200408053 (ίο) 發明說明續頁 描述中描述,其中: 圖1顯示當使用傳統鈦/氮化鈦方法和平行鈦/傳統氮化鈦 方法形成障礙金屬層時可獲得的障礙金屬層的剖面圖; 圖2顯示當使用IMP鈦/CVD氮化鈦方法及_?鈦/IMp氮化 鈦方法形成障礙金屬層時可獲得之障礙金屬層的剖面圖; 圖3顯示取決於顯示在圖1之障礙金屬層的剖面上之失敗 單元之剖面圖的TEM ; 圖4顯示取決於顯示在圖2之障礙金屬層之剖面,失敗單 元之剖面圖的TEM ; 圖5A和圖5B顯示用以解釋因為根據顯示在圖3和4之剖面 發生之降低的電導(1/R)特性,裝置之功能失敗的特徵; 圖6A至圖6C係為半導體裝置之剖面檢視圖’其用以描述 製造根據本發明之較佳具體實施例的半導體裝置的方法; 以及 圖7A至圖7C係為說明取決於AC偏壓電源’障礙金屬層之 剖面的半導體裝置的剖面檢視圖。 圖式代表符號說明 12、 11、 102 内 層 絕 緣 膜 10、 20、 100 半 導 體 基 材 14、 24、 104 接 觸 洞 16a 、26a 、106a 鈦 膜 16b 、26b 、106b 氮 化 鈥 膜 26、 106 障 礙 金 屬 層 108 嫣 層
Claims (1)
- 200408053 拾、申請專利範圍 1. 一種在半導體裝置中形成金屬線之方法,其包括下列步 驟: 在半導體基材上形成内層絕緣膜,在其中形成給定結 構; 蝕刻該内層絕緣膜以形成接觸洞; 在接觸洞之内表面上形成障礙金屬層,其中障礙金屬 層之剖面藉由施加AC偏壓電源以具有在該接觸洞底部 之凹剖面而決定;以及 形成接觸插頭,藉由其該接觸洞被埋葬且之後在整個 結構上形成金屬線。 2. 如申請專利範圍第1項之方法,其中該AC偏壓電源係為 200至 500 瓦。 3. 如申請專利範圍第1項之方法,其中藉由使用單一室之離 子金屬電漿方法形成該障礙金屬層,以具有鈦膜和氮化 鈦膜之堆疊結構。 4·如申請專利範圍第3項之方法,其中藉由施加1.5至3.0千 瓦之DC電源、1.5至3.0千瓦之RF電源和200至500瓦之AC偏 壓電源,在室壓保持在10至50毫陶爾的狀態中沉積該鈦 膜厚度為100至500埃。 5.如申請專利範圍第3項之方法,其中該膜藉由實施下列步 驟而形成以具有第一和第二氮化鈦膜之堆疊結構: 在該室之情況與鈦膜沉積情沉保持相同的狀態下注入 氮氣至該室中,以沉積該第一氮化欽膜; 防止氮氣注入室中,以在第一氮化鈦膜上沉積鈦膜; 200408053 申請專利範圍續頁 以及 實施使用氮氣之退火方法,以改變該鈦膜至第二氮化 鈥膜。 6·如申請專利範圍第1項之方法,其中該障礙金屬層藉由使 用第一和第二室之離子金屬電漿的方法形成具有鈦膜和 氮化鈦膜之堆疊結構。7. 如申請專利範圍第6項之方法,其中藉由施加1.5至3.0千 瓦之DC電源、1.5至3.0千瓦之RF電源和200至500瓦之AC偏 壓電源,在第一室壓保持在10至50毫陶爾的狀態中,以 100至500埃厚度沉積該鈦膜。 8. 如申請專利範圍第6項之方法,以在第一室相同情況但是 額外地鈦膜沉積其上之半導體基材移到氮氣被注入之該 第二室下,該氮化鈥膜在飲膜上沉積。
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US7037837B2 (en) * | 2004-07-29 | 2006-05-02 | Texas Instruments Incorporated | Method of fabricating robust nucleation/seed layers for subsequent deposition/fill of metallization layers |
US20060024953A1 (en) * | 2004-07-29 | 2006-02-02 | Papa Rao Satyavolu S | Dual damascene diffusion barrier/liner process with selective via-to-trench-bottom recess |
DE102007004884A1 (de) * | 2007-01-31 | 2008-08-14 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung einer Metallschicht über einem strukturierten Dielektrikum durch stromlose Abscheidung unter Anwendung einer selektiv vorgesehenen Aktivierungsschicht |
US20080254613A1 (en) * | 2007-04-10 | 2008-10-16 | Applied Materials, Inc. | Methods for forming metal interconnect structure for thin film transistor applications |
US10002834B2 (en) * | 2015-03-11 | 2018-06-19 | Applied Materials, Inc. | Method and apparatus for protecting metal interconnect from halogen based precursors |
CN114927413B (zh) * | 2022-07-19 | 2022-11-04 | 广州粤芯半导体技术有限公司 | 粘附金属层的溅射方法及半导体器件的制造方法 |
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JPH06158299A (ja) * | 1992-11-19 | 1994-06-07 | Hitachi Ltd | 薄膜形成法及び装置並びに集積回路装置 |
JPH08107087A (ja) * | 1994-10-06 | 1996-04-23 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
US5712193A (en) * | 1994-12-30 | 1998-01-27 | Lucent Technologies, Inc. | Method of treating metal nitride films to reduce silicon migration therein |
US5962923A (en) * | 1995-08-07 | 1999-10-05 | Applied Materials, Inc. | Semiconductor device having a low thermal budget metal filling and planarization of contacts, vias and trenches |
JPH10237639A (ja) * | 1997-02-24 | 1998-09-08 | Anelva Corp | 集積回路用バリア膜を作成するスパッタリング装置 |
KR100257154B1 (ko) * | 1997-06-25 | 2000-05-15 | 김영환 | 반도체 소자의 금속 배선 형성 방법 |
KR100273989B1 (ko) * | 1997-11-25 | 2001-01-15 | 윤종용 | 반도체장치의콘택형성방법 |
KR100484253B1 (ko) * | 1998-06-27 | 2005-07-07 | 주식회사 하이닉스반도체 | 반도체 장치의 타이타늄막 형성방법 |
JP4074014B2 (ja) * | 1998-10-27 | 2008-04-09 | 株式会社東芝 | 半導体装置及びその製造方法 |
US6451181B1 (en) * | 1999-03-02 | 2002-09-17 | Motorola, Inc. | Method of forming a semiconductor device barrier layer |
EP1094504A3 (en) * | 1999-10-18 | 2001-08-22 | Applied Materials, Inc. | PVD-IMP tungsten and tungsten nitride as a liner, barrier, and/or seed layer |
US6423636B1 (en) * | 1999-11-19 | 2002-07-23 | Applied Materials, Inc. | Process sequence for improved seed layer productivity and achieving 3mm edge exclusion for a copper metalization process on semiconductor wafer |
US6387800B1 (en) * | 1999-12-20 | 2002-05-14 | Taiwan Semiconductor Manufacturing Company | Method of forming barrier and seed layers for electrochemical deposition of copper |
US6294458B1 (en) * | 2000-01-31 | 2001-09-25 | Motorola, Inc. | Semiconductor device adhesive layer structure and process for forming structure |
US6562715B1 (en) * | 2000-08-09 | 2003-05-13 | Applied Materials, Inc. | Barrier layer structure for copper metallization and method of forming the structure |
US6652718B1 (en) * | 2001-01-30 | 2003-11-25 | Novellus Systems, Inc. | Use of RF biased ESC to influence the film properties of Ti and TiN |
JP2003115535A (ja) * | 2001-10-04 | 2003-04-18 | Hitachi Ltd | 半導体集積回路装置 |
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TWI314765B (en) | 2009-09-11 |
US20030119325A1 (en) | 2003-06-26 |
KR100440261B1 (ko) | 2004-07-15 |
KR20030053322A (ko) | 2003-06-28 |
JP4657571B2 (ja) | 2011-03-23 |
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