SU983744A1 - Information display device - Google Patents

Description

one . . The invention relates to display devices with a light profile indicator and can be used to indicate a large number of KG parameters in various automated systems. There are known display devices with a light-profile pointer, which contain two groups of information buses, an input register, a decoder, indicator elements, keys, and isolation elements, for example, the THRD diodes closest to the proposed technical entity is; a device for indicating, containing a scrambler with a scaling circuit, connected to the output of the input register, keys connected to, with indicator elements, logic elements and decoupling elements G21. The disadvantages of the known devices are the uneven load on the keys, the lack of accuracy of the display and, in addition, the inability to display the parameters expressed in codes when individual devices are combined into multi-channel indicators to display a large number of parameters. The aim of the invention is to improve the accuracy of the device. The goal is achieved by the fact that the device for displaying information containing serially connected first memory block, key block, decoder block, code-analog converter connected to linear gas-discharge indicators, synchronization block connected to the input of the first memory block, inputs which are the information inputs of the device, the information reset unit, the input of which is connected to the second input of the key block, the third input of which is the control input of the device, the output of the reset unit formations connected to

the inputs of the first memory block and the synchronization block whose inputs are the clock inputs of the device are entered in series the second memory block, the AND block and the switch, the output of which is connected to the second key block input, the first input of the second memory block is connected to the output the information reset unit and the second input are the control input of the device, the inputs of the second memory block are the clock inputs of the device.

FIG. 1 shows a block diagram of the device; in fig. 2 - 15 diagrams of device operation. The device contains the first 1 memory block, the 2 key block, the 3 decoder block, the analog code converter k, the linear gas-discharge indicators 5, the synchronization block 6, the reset block 7, the second 8 memory block, the And block 9, the switch 10, control input 11; FIG. 2 marked: 12-1A. The distribution of clock pulses on channels; 15-19, 20-2, and 25-29 — memorizing the sync pulses by the 2nd memory block; 30-3 - formation of signals by the block of elements And 35-39 - formation of commands from the switch output, kQ-kk - formation of commands by the reset unit. The device works as follows. In the initial state, the input registers of the first and second memory blocks 1 and 8 are set to the zero state. The key block 2 is closed, and no information is received at the input of the decoder 3. The information to be displayed on the display panel is sent to the first inputs of the first memory block for each of the channels from 1 to n at arbitrary times during one clock cycle. The moment of arrival of the displayed information in any of the channels corresponds to the timing of the sync pulse to the corresponding channel from 1 yo n of the synchronization unit 6. FIG. 2 (positions 12-14) shows the distribution of sync pulses for the case of channels and one clock cycle consisting of 5 bursts, information on each of the channels. At the moment of arrival of a clock pulse on any of the channels, the synchronization unit generates a command to write incoming information to the input of memory block 1 in one of the registers on this channel.

Simultaneously, the clock pulses arriving on each of the channels are stored in the registers of the second memory block 8 and are stored in them until the end of the clock. FIG. 2 (position 15-19, 20-2A, 25-29) shows the memorization of clock pulses by the second memory block for each of the channels.

Claims (2)

If there are consecutive coincidence of sync pulses from each of the information parcels from the output of block 9 elements I, the resolution goes to switch 10 (Fig. 2, position 30-3), which generates commands to switch keys (Fig. 2, position 25-39). 2. At the same time, simultaneous reading of information stored in the first, second, etc. is performed. registers of the memory block for each of the channels. The decoder unit and the code-analogue transducer form the control signal to the linear gas-discharge indicators 5. At the moment when the switch 10 issues a command for switching over the leading edge of this pulse, the reset unit 7 generates a pulse that sets the input registers to which the previous parcel information was written to zero, thus preparing the device circuit for the next indication cycle. Taking into account that the device can operate only in the presence of sync pulses on all channels, the device has a control input 11 to which, when it is necessary to turn off any channel due to lack of information (or malfunction), a prohibitory signal is provided, blocking the corresponding channel in the block 2 keys and setting the registers of the given channel in the second memory block to the state of logical 1, thereby disconnecting the given channel. Thus, the introduction of the second memory block, the AND block and the switch allows synchronization of the display of information arriving at arbitrary moments of time during the cycle for each of the series of informational messages, which allows a comparative analysis of the sequence of incoming information for each from channels and. thereby increasing the accuracy of the display of incoming information. Apparatus of the Invention A device for displaying information comprising serially connected first memory block, key block, decoder block, code-analog converter connected to linear gas-discharge indicators, synchronization block connected to the input of the first memory block whose inputs are information inputs of the device, the information reset unit, the input of which is connected to the second input of the key block, the third input of which is the control input of the device, the output of the information reset block is connected to the inputs of the first memory block and the synchronization block, whose inputs are the clock inputs of the device are ordered so that, in order to improve the accuracy of the device, the second memory block connected in series is inserted into it, And the switch, the output of which is connected to the second input of the club block, the first input of the second memory block is connected to the output of the information reset unit, and the second input is the control input of the device, the inputs of the second memory block are clock inputs. Sources of information taken into account in the examination 1. The author's certificate of the USSR Vf 2TS76A9, cl. G 06 K 15/18, 1968. 2. USSR author's certificate number 318968, cl. G 06 K 15/18, 1970 (prototype). П П П П П П n n П П П П П ( 2021 222321 / 25. 26272829 W31 32JJ