SU935936A1 - Apparatus for syncronization of pulse signals - Google Patents

Description

(St) DEVICE FOR SYNCHRONIZATION OF PULSE SIGNALS

one

The invention relates to computing and can be used in multichannel automatic control and regulation systems, and also to form one or several signals of a certain duration from a pulse front.

The known device for synchronizing signals used in computing and processing systems, information, containing the source (generator) of clock pulses, switch, triggers, elements And and

OR 1 and Cr.

The disadvantages of these devices are their comparative complexity and lack of speed.

Closest to the invention is a device for sinuronization of pulse signals, comprising a clock pulse generator, a switch, triggers, an AND and OR element, and the channel outputs are combined

by the OR element, the single input of the tri1-ger record of each channel is connected to the channel input, the single outputs of the recording triggers. storing and resetting each channel is connected to the inputs of the corresponding AND elements, the output of which is connected to the corresponding inputs of the flip-flops. The pulses generated by the switch, spaced apart in time, do not mutually overlap at the second inputs of the elements And.

The disadvantages of this device are the presence of a switch that generates working pulses, the impossibility of working with signals that have a longer duration (short information impulses are necessary for the device to work, since in this case false

20 alarms, as well as low speed (information may be given with a delay of four clock pulses).

The aim of the invention is to simplify the device and increase its speed.

This goal is achieved by the fact that in a device for synchronizing pulse signals, containing a clock generator, recording, storage, reset triggers and an OR element whose output is a device output, in each of the two channels a single output of recording trigger is connected to the storage trigger information input the same channel, the single output of the hrenepi trigger is connected to the information input of the reset trigger, the single output of the reset trigger is connected to the zero input of the recording trigger, the information input It is connected to a device constant 1 bus, and a clock input is connected to a corresponding bus of device information signals, the clock inputs of the storage trigger and reset trigger are connected to the clock pulse output, the single output trigger of the first channel recording trigger is connected to the zero input of the second channel trigger trigger, the unit output of which is connected to the zero input of the storage trigger of the first channel, the unit outputs of the reset triggers, the first and second channels are connected to the inputs of the OR element.

FIG. 1 is a block diagram of a device for synchronizing pulse signals; in fig. 2 - timing charts of the device at different phases of the arrival of in-. formational signals F. and fj

The device consists of two channels and contains recording triggers 1 and 2 storage triggers 3 and, reset triggers 5 and 6, and the element OR 7, output 8 of which is the output of the device.

The device works as follows.

In the initial state, all the triggers are in the zero state. When the recordings of the 1 and 2 fronts of the information signals are written to the trigger inputs of the triggers, the triggers go into one state, since the signals that allow the triggers to switch to one state are constantly present at their information inputs; At the same time, the potential at the single output of the trigger of record 1 enables the operation of the storage trigger 3 on the information input and prohibits the operation of the storage trigger 4 on the zero input. With the arrival of the front of the clock frequency supplied simultaneously to the clock inputs of the trigger of the clock pulse generator, the storage trigger 3 goes into one state,

enabling the reset trigger 5 on the information input. The front of the next clock pulse triggers the storage 3 to the zero state, and the reset trigger 5 to the unit state. Potential at the single output, reset trigger 5 sets record trigger 1 on the zero input to the initial state. The zero state of recording trigger 1 removes the prohibition on the zero input of the storage trigger 4, and with the arrival of the next clock edge, the storage trigger goes to the single state allowing the information input to operate the reset trigger 6, simultaneously blocking the zero input trigger of storage 3 With the same front clock frequency reset reset 5 is set to zero

allowing the zero input to receive the following information into the recording trigger 1 and ending the formation of the output pulse at the output 8 of the element OR 7. With the arrival of the next clock edge, the storage trigger goes to the zero state allowing the zero input to work the storage trigger 3, and the reset trigger 6 goes to in one state, set by zero input to the initial state trigger record 2 and is fed to the input of the element OR 7. The next edge of the pulses of the clock frequency is the reset trigger b set to zero with This stops completing the formation of output 8 of the element OR 7 of the output impulse, pulse. of the second channel, and allows for zero input to receive the recording trigger 2. In all other cases, the device works similarly.

Claims (2)

J-K or D-type triggers can be used in the device. Information signals can come in the form of short pulses, and in the form of potentials. At the same time, pulses of equal duration over the period of such a frequency are generated at the output. The information frequency F must satisfy the condition F T IT, where f is the clock frequency. The maximum delay in the delivery of pulse from one channel is equal to the period of the clock frequency. The proposed device for synchronizing pulse signals is advantageously different from the known one, as the number of logic elements used is reduced, as a result of which the volume taken up by the device is reduced, and its reliability is increased. Refusal from the switch allows you to delay the output of the information pulse not by a variable (from 1 to pulses of the clock frequency, and not more than 1 period taK of the frequency of frequencies in one channel, which significantly increases the speed of the device and expands the scope of its application. The device can be used for counting asynchronous information flows by a single counter (in multi-channel digital recording devices), for controlling a reversible counter (in automatic control systems and computing; one channel of the device can be van as a driver from one front of the information signal of a series of timed and time-shifted control pulses with a minimum delay time (for example, for stopping the counter, recording its contents in the register and resetting the counter, in automatic control systems) equipment. In this case, the pulses are removed from the single outputs of the recording trigger, auxiliary circuit and reset trigger. 6 The invention The device for synchronizing pulse signals, comprising a clock pulse generator, recording, storage, reset triggers and an OR element, the output of which is an output of a device, characterized in that, in order to simplify the device and increase its speed, two channels, the single output of the recording trigger is connected to the information input of the storage trigger of the same channel, the single output of the storage trigger is connected to the information input of the reset trigger, the single output of the reset trigger En to the zero input of the recording trigger, the information input of which is connected to a device constant value bus 1, and the clock input to the corresponding device information signal bus, the clock inputs of the storage trigger and reset trigger are connected to the output of the clock generator, the first output recording trigger of the first channel connected to the zero input of the storage trigger of the second channel, the single output of which is connected to the zero input of the storage trigger of the first channel, the single outputs of the trigger reset of the first and the second channel is connected to the inputs of the element OR. Sources of information taken into account in the examination of T, USSR Author's Certificate No. 22li898, class, C 06 F l / 0t, 1967. 2. USSR author's certificate, No. 378830, cl. S About F 1/04, 1971. 3, USSR Copyright Certificate No. 560218, cl. C 06 F 1 / OA, 1977 (prototype).