SU924902A2 - Self-synchronizable discrete information receiving device - Google Patents

Description

() DEVICE FOR RECEPTION OF SELF-SYNCHRONIZING DISCRETE INFORMATION

I

The invention / relates to a technique for transmitting discrete information and can be applied in data transmission systems using the asynchronous principle.

BY MAIN auth. St. No. 836814, a device for receiving self-synchronizing discrete information is known, comprising a series-connected unit: signal processing, a memory element, a shift register, a switching unit, and a decoder, as well as a series-connected receiver, accumulator, and clock selector, whose output is connected to the enable input of the switching unit, wherein the combined inputs of the receiver and the signal processing unit are input to the device.

However, the known device has low noise immunity due to a significant number of undetectable errors.

The purpose of the invention is to improve noise immunity.

To achieve this goal, three time selectors, two inverters, an AND element, an additional memory element, a delay element, and an OR element, whose output is connected to the recording input of the additional, memory element, to the erase input of which is connected through the delay element, are entered into the device. the output of the clock selector, and you-. The input of the additional memory element is connected to the prohibiting input of the kommatization unit, while the outputs of the signal processing unit through the first and second time selectors, as well as through the first and second inverters are connected respectively to the first and second inputs of the OR element and the first and second inputs of the AND element whose output through the third time selector is connected to the third input of the element OR. S9 FIG. 1 shows the structural electrical protection of the device; in fig. 2 time diagrams for his work. The device for receiving self-synchronizing discrete information comprises a signal processing unit 1, a receiver 2, a storage unit 3, a shift register k, a switching unit 5, a clock signal selector 6, a memory element 7, a decoder 8. The receiver 2 consists of a block 9 for recovering significant recovery moments (SQMM a) signal and driver 10 pulses of a given duration, the signal processing unit 1 consists of a selector 11 positive packages and a selector 12 negative packages. The device also includes first, second, and third time selectors 13, 1, and 15. OR element 16, AND element 17, first and second inverters 18 and 19, additional memory element 20, and delay element 21. The device works as follows. The self-synchronizing pulse ternary sequence (Fig. 2) is formed on the transmitter from the binary sequence A according to the following law: К Х || To (the index corresponds to the sequence number of the significant characteristic modulation moment of the transmitted signal,), is fed to the inputs of receiver 2 and signal processing unit 1 (Fig. 2cO). In block 9 of the signal receiver 2, the edges of the incoming signal are highlighted. Pulses are set to the input of a predetermined duration (Fig. 25). Pulse generator 10 of a given duration is determined by the ZHMV pulse and pulses of a given duration, which are fed to the input of drive 3 (Fig. 2), are completed. whose code combination in accumulator 3, the synchronization signal selector 6 fixes it and outputs the information release signal (FIG. 2i) to the input of the switching unit 5. recorded in the shift register K. The signal processing unit selects 8 received sequences of positive and negative sections At the input of the selector 11 positive messages, a pulse (Fig. 23) appears when there is a positive message in the self-synchronizing sequence, and at the output of the selector 12 negative messages (Fig. 2e) - the presence of a negative premise. The signals from the outputs of the selectors 11 and 12 positive and negative parcels are received respectively on the S-. and the R inputs of memory element 7 performed on an L5-tri1-ger, where they are converted into a binary information sequence. At the same time, signals from the outputs of block 1. The signal processing is fed to the inputs of the first and second time selectors 13 and 1 and to the inputs of the first and second inverters 18 and 19. From the outputs of the first and second inverters 18 and 19, signals through the element 17 arrive at the input of the third time signal. selector 15. The first, second and third time selectors 13 1 and 15 work if the duration of a positive, negative or neutral (zero) premise, respectively, is less than the specified selection time, which is more likely to lead to an error. When any of the selector selectors 13, 15 are triggered, the signal from the output of the triggered time selector through the element OR 1b is fed to the record of the additional memory element 20. In this case, an additional blocking signal is output from the output of the additional memory element 20 to the inhibit input of the switching unit 5, so that the code combination from the shift register k is not transmitted to the decoder 8. The additional memory element 20 is reset (reset) the signal from the delay element 21, which is triggered by the trailing edge of the sync signal from the sync signal selector 6. From the output of the memory element 7, the binary information (Fig.) Is sequentially inputted to the shift register U. By the signal from the output of the sync signal selector b, this information sequence through the switching unit 5 enters the decoder 8, where it is converted into a message sign. Thus, the proposed device for receiving self-synchronizing discrete information that is part of the data transmission equipment, when transmitting short messages, allows to ensure high reliability. Probability of erroneous reception of a code combination. decreases 2-5 times.

Claims (1)

Invention Formula A device for receiving self-synchronizing discrete information on aut. St. If 836814, characterized in that, in order to improve noise immunity,. it has three time selectors, two inverters, an AND element, an additional memory element, a delay element and an OR element, an output G2 9026 which is connected to the recording input of the additional memory element, to the recording input of the additional memory element, the output of the clock selector is connected to the erasing input of which through the delay element, and the output of the additional memory element is connected to the inhibitory input of the switching unit; "About the signal processing unit through the first and second time selectors, as well as through the first and second inverters are connected respectively to the first and second inputs of the element 15 OR 1 to the first and second inputs of the AND element whose output through the third time selector is connected to the third input of the OR element. tl9. /  fti tiof o -ff 6 s 1 g 5 z one i I 6 678