SU470924A1 - Receiver in asynchronous interface systems for digital signals with two-way time shifts - Google Patents

Description

This invention relates to multichannel communication systems and is intended to transmit asynchronous pulse sequences.

A receiving device in asynchronous interface systems of digital sigpals with two-way time shifts is known, containing an OR circuit connected to the NO circuit, the output of which is connected directly to the clock input of the memory node, and through a phase detector connected to an auto-tuning generator, and with automatic frequency control - to another input of the memory node, as well as a decoder of commands about the presence of time shifts.

However, the known device has a low reliability of transmitted messages, due to the fact that the distortion of any command about the presence of a time shift causes a frame alignment failure in a component system of a lower order.

In order to increase the reliability of the transmitted messages in the proposed device, the outputs "plus and" minus the decoder of commands about the presence of time shifts are connected respectively through additional circuits "NO to the first inputs of the circuits" OR and "NO, and through the corresponding counters the number of commands connected to the prohibiting inputs “NO” circuits connected to the second inputs of the “OR” and “NO.

FIG. 1 shows a functional diagram of the proposed receiving device; in fig. 2 - functional dependencies that clarify its work.

The information signal from the output of the channel distributor (Fig. 1) under the action of

the clock frequency is recorded in the memory node 1 and read out by the pulse sequence from the output of the generator 2 with automatic frequency control, which is controlled by the phase detector 3. To the inputs of the latter, pulse sequences with a write and read frequency are supplied. The signal of the time shifts arrives at the decoder of commands 4 in the form of time shifts (+ or -). On the command of the presence of a positive time shift, an information recording prohibition signal is generated in the storage node arriving at the NO 5 prohibitory entry through the open additional circuit NO 6. The command of the presence of a negative time shift produces an additional information symbol recording signal in the storage node, the incoming using the scheme "OR 7 through an open additional scheme

“NO 8.

At the same time, signals from the output of the command decoder are fed to counters 9 and 10 of the number of commands. The signal at the output of the counter records the presence of three consecutive commands of the same character. According to this, the signal with the help of the additional scheme "NO 6 or 8 (depending on the sign of the distorted command) restores the original command.

FIG. 2, a shows the change in the phase of the read frequency relative to the recording frequency Af (/), and FIG. 2,6 - the corresponding structure of commands formed in the transmitting device. If the phase difference does not reach the reading period, alternate commands are formed: +. - +. - +, etc., and if the phase difference reaches a period, then two identical commands are formed: +, + or -, - (depending on the sign of the phase difference).

If one of the two alternating commands is distorted, the same-character structured commands are formed. If one negative command is distorted (Fig. 2, c), strong positive commands are formed, and if one positive command is distorted, strong negative commands are formed (Fig. 2, d). With normal (undistorted) signaling about the presence of time shifts, there are no solid commands. On this basis, any distortion of alternating commands can be detected and corrected, and

Since systems with bilateral time shifts are characterized by long alternations of commands of the same character, practically all the distortions of commands about the presence of time shifts can be corrected in the receiver.

Subject invention

A receiver in the asynchronous interface systems of digital signals with two-way time shifts, which contains the OR circuit connected to the circuit.

"NO, the output of which is connected directly to the clock input of the memory node, and via a phase detector connected to a frequency-controlled generator, and a frequency-controlled generator to another input of the memory node, as well as a time shift decoder, characterized in that , in order to increase the reliability of transmitted messages, the outputs "plus and minus decoder

commands about the presence of time shifts are connected, respectively, through additional schemas "NO to the first inputs of the OR or NO circuits and through the corresponding counters of the number of commands connected to the forbidding

the inputs of additional circuits "NO, are connected to the second inputs of the circuits" OR and "NO.

ve.i

+ - + - + - + - + - + - +

- + - + - + - + - + (+ f + - + + + ... + - +

+ - + - + - +

distorted team

+ - + - + - +

isna nena /) command