SU1427583A1 - System for asynchronous matcning of pulse streams - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to increase the reliability of the system. The system contains on the transmitting side - transmitting channel devices 1, each of the driver 2 clock pulses, the transmitting selector 3 of the synchronization signal, the transmitting control unit 4, the frequency divider 5, the transmitting unit 6 of the controlled delay, the transmitting unit 7 of the primary memory time detector 8 and interdiction blocks 9, 10, and on the receiving side - receiving channel devices 11, -11x consisting of each of the receiving selector 12 of the sync terminal, receiving unit 13 of the controllers of the 14 and 15 h of the Goth, receiving block 16 ugfavl Of the dynamic memory block 17, the prohibition blocks 18 and 19, and the phase-locked loop 20 of the partial memory: "On the transmitting side negative and semi-modular inserts are performed, after which the pulsed flow enters the receiving-side. S // Do jL

Description

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Here cycles are detected in which inserts are inserted, and depending on whether positive or negative inserts are detected, one of two pulse sequences is formed to control the process.

and -off inserts entered and. transmitting side. After that, the first symbols of the clock signals are restored and the recovered pulse stream enters the corresponding system output. 3 il.

one

The invention relates to telecommunications, in particular, to devices for transmitting and receiving discrete messages with asynchronous inputs and information output, and can be used in the development of an asynchronous device for matching pulse rates.

flows on the transmitting and receiving station I

ronah.

The purpose of the invention is to increase the reliability of the system.

Figure 1 shows the structural electrical circuit of the asynchronous interface system of pulsed flows; figure 2 - timing charts of the transmitting channel device; on fig.Z - timing charts of the receiving channel devices and.

The asynchronous impulse streams system contains on the transmitting side k transmitting channel devices 1 (where, 2, ...) s each channel device contains a shaper of 2 clock pulses, each channel device except the first one contains a transmitting selector 3, a clock signal, a transmitting unit four; control, the first frequency divider 5, the transmitting unit 6 at the controlled

The asynchronous interface system of pulsed POT-OKOV operates as follows.

On the transmission side for each

5, there is a transmitting channel device 1j, the input of which is the input of the corresponding pulse system flow. From the input of the transmitting channel device 1,

10, the pulse stream enters the input of the imaging unit 2, clock pulses and the output of the transmitting channel device 1 (. The former 2, clock pulses extracts the spectral component of the clock frequency from the pulse flow 15 and generates read clock pulses for the other channel devices.

For the remaining impulse streams

20 we consider the work on the example of the transmitting channel device 1. Figure 2 shows time diagrams at characteristic points of the transmitting channel device 1.2.

25 From the input of the transmitting channel

the device 1, a pulse stream is fed to the input of the clock 2 clock pulses and to the input of the transmitting selector 3} of the clock signal. The formation delay, the transmitting unit 7 - the driver 2 clock pulses of the special memory, the time detector first 9ts and the third 10, prohibition blocks; and on the receiving side - k-1-receiving channel devices 11ц (where, 2.,.), each receiving channel 5 device contains a receiving selector 12 | synchronization signal, the control receiving unit 13, the second 14, and the third 15i frequency dividers, the receiving unit 16 | controlled delay, the receiving unit 0 M of dynamic memory, the second block 18 of the ban, the fourth block 19ts. ban, block 20t phase-locked loop (PLL).

The pulse frequency spectral component from the pulse stream and generates clock pulses, which are used for timing the operation of blocks of the transmitting channel device 1.

The pulse stream from the input of the transmitting selector 3 of the sync signal passes through the shift register located in it, and is fed to the transmitter of the transmitting selector 3 of the sync signal and then to the input of the block 7 of the transmitting dynamic memory (Fig. 2a). From the output of the transmitting selector 3

The asynchronous interface system of pulsed POT-OKOV operates as follows.

On the transmission side for each

a pulsed stream there is a transmitting channel device 1j, whose input is the input of the corresponding pulsed stream of the system. From the input of the transmitting channel device 1,

the pulse flow enters the input of the imaging unit 2, clock pulses and the output of the transmitting channel device 1 (. The former 2, the clock pulses extracts the spectral component of the clock frequency from the pulse flow and generates read clock pulses for the other channel devices.

For the remaining impulse streams

Let us consider the work on the example of the transmitting channel device 1. Figure 2 shows the time diagrams at characteristic points of the transmitting channel device 1.2.

From the input of the transmitting channel

the device 1, a pulse stream is fed to the input of the clock 2 clock pulses and to the input of the transmitting selector 3} of the clock signal. Shaper 2 clock pulses highlighted -

The pulse frequency spectral component from the pulse stream and generates clock pulses, which are used for timing the operation of blocks of the transmitting channel device 1.

The pulse stream from the input of the transmitting selector 3 of the sync signal passes through the shift register located in it, and is fed to the transmitter of the transmitting selector 3 of the sync signal and then to the input of the block 7 of the transmitting dynamic memory (Fig. 2a). From the output of the transmitting selector 3

clock signal clock pulses are fed to the input of the overflowing unit 4 controls.

The first frequency divider 5 divides the clock frequency by m + n. As a result, pulses with a frequency equal to the cycle frequency in the pulse flow are formed at its output, and are fed to the input of control unit 4, which generates pulses for setting the first frequency divider 5 to the initial state, thereby providing its in-phase mode. In addition, the transmitting control unit 4 generates pulses for controlling the rate matching, which are removed from the second output and fed to the input of the transmitting unit 6 of the controlled delay and the input of the third prohibition unit (Fig. 26).

Using the write clock pulses received from the clock clock generator 2 through the third prohibition block 10 at the input of the transmitting dynamic memory unit 7, the incoming pulsed flow pulses are recorded into the transmitting dynamic memory unit 7, and with the help of read clock pulses the generator 2 clock pulses through the first block prohibition 9j to the first input of the transmitting unit 7 of the dynamic memory, reads the recorded pulses. At the same time, depending on the sign of i, the difference in the write speeds and readings, positive or negative inserts are periodically inserted to match the speeds when the change of time intervals to the melody by pulsed write and read sequences reaches the readout period. This moment is detected with the help of a temporary detector S, at the corresponding output of which potential 1 is formed and fed to the corresponding input of the first 9 or third 10 blocks

ban. From this moment on, the corresponding block 9 or 10 of the prohibition enters the mode of waiting for the impulse of matching speeds (figv - 2m).

When f J fg, where fj and f. - write and read frequencies, respectively, negative inserts are entered.

Speed matching pulse from the second output of the transmitting unit

about with.

5 5

0

control enters the input of the third block lOj of the prohibition and if there is a pulse at its input from the temporary detector 8 it prohibits the passage of one clock pulse of recording to the input of the block 72 of the transmitting dynamic memory. In this way, negative insertion is performed.

When f, f (.- the positive set-ups are entered. The impulse is matched to the speeds from the output of the transmitting unit 4. The control enters the input of the transmitting unit 6 of the controlled delay, is delayed by it until the corresponding character is read from the transmitting unit 7 of the dynamic memory, enters the input of the first block 92 of the prohibition and in the presence of H; -i pulse from the temporal detector 8 at the input of the first block 9 of the ban prohibits the passage of one clock pulse read to the ihfl of the transmitting block 7 of the dynamic G1a--. CTA vvedr.nke positive inserts. Next the pulse stream is supplied to the output channel transmitting device 1.

On the receiving side, the first impulse flow is not needed in the kpkpay or processing, so the channel.: Device for Hei o is absent,. For the remaining impulse flows, paccMCf RIM work on the example of the receiving channel device 11. Fig. 3 shows time diagrams p characteristic points of the receiving channel device 11 ,,.

The impulse flow from the input of the receiving selector 12 of the sync signal passes through the shift register located in it, and arrives at the output of the receiving selector 12 of the synchronizing signal and then to the input of the dynamic memory receiving unit 172 (Fig. 3a). From the output of the receiving selector 12.2 of the clock signal, the clock pulses are fed to the input of the receiving unit 13 of the control.

Claims (1)

The second 14.2 and the third 15, the frequency dividers divide the frequency by m + n. As a result, their outputs generate pulses with a frequency equal to the ckk following frequency in the pulsed flow and arrive at the inputs of the receiving unit 13, controlling . The receiving control unit 13 generates pulses for setting the second 14 and third 15 frequency dividers to the initial state, thereby ensuring their normal phase operation. The second divider 1, the frequencies are included in the search circuit CHHxpoHHSNja of the receiving unit 13, and the third divider 15. In the interval, the duplicate inserts are ruled 1. Thus, the negative inserts entered on the transmitting side are eliminated and the first symbols of the sync signals are restored. The recovered pulse flow enters the corresponding system output. Invention Formula ten i tots - in the chain of synchronization control. ; The receiving unit G3.2 of the control of the obsession: the cycles in which the inserts are inserted determines the nature of these inserts (positive or negative) and, depending on whether the insertions are positive or negative, forms one two sequences of pulses, each device (where, 2, ...), each to control the exclusion process, each of which contains a shaper entered on the transmitting side of the positive or negative inserts, respectively. Pulse sequences for destroying, each transmitting channel exclusion of positive inserts of the pastor device, except the first one, is closed at the output of the receiving b: current 3 of the control and fed to the input of the second block 18, which is forbidden at the moment of entering the receiving block 17 of the uni the device, the second and the third memory of the positive insert-outputs, are connected respectively with ki, prohibiting each pulse from passing one clock pulse through the second block 18, prohibiting the first input of the receiving block 17 of the dynamic memory (fig.Zb, g). In this case, the positive insertion in the receiving block 17.2 of the dynamic memory is not recorded. Thus, an asynchronous impulse flow conjugation system is implemented, which contains on the transmitting side k transmission channels 1 and 1 pulses, whose input is the signal input of the corresponding transmit channel, the dynamic memory transmitting unit, the first output of which is the output of the corresponding transmitting terminal. the first and second inputs of the temporary detector, and the output of the first prohibition block are connected to the first input of the transmitting dynamic memory block, and on the receiving side - k-1 (where k 1,2, ...) receive channel devices, each of which contains the receiving the dynamic memory unit, to the first input of which the output of the second inhibit unit is connected, the first output of the dynamic memory unit is connected to the first input of the phase locked loop (FALCH) unit, and the second output is the output of the corresponding channel receiving device, which differs from so that, in order to increase the reliability of the system, the signal input of the first transmitting channel oral positive inserts. The pulse sequence / elimination of negative inserts is formed at the output of the receiving unit 13, the control and through the receiving unit 16 of a controlled delay, by which each pulse is delayed until the corresponding negative insert is read from the receiving unit 17 of the dynamic memory, to the input of the fourth prohibition unit 19, banned by everyone 35 40 the first and second inputs of the temporary detector, and the first input of the forward dynamic memory block is connected to the output of the first interdiction block and on the receiving side - k-1 (where k 1,2, ...) receive channel devices, each of which contains the dynamic memory receiver unit, to the first input of which the output of the second prohibition unit is connected, the first output of the dynamic memory unit is connected to the first input of the phase locked loop (FALCH) module, and the second output is the output of the corresponding channel receiver device, different Thu , To improve the reliability of the system ti, a signal input of the first transmitting channel mouth the impulse of the passage of one clock is connected to the first output pulse through the fourth block 19 of the prohibition on the input of the block 17 of the receiving dynamic memory (Fig.Zv, d). In this case, when reading from the receiving block 17 of the dynamic memory, a duplicate insert is inserted into the pulse flow at the place of the negative insert, i.e. the clock interval in the cycle is restored, and when converted to a serial code by the same pulse, which arrives at the fourth input of the receiving block 17 of the dynamic memory, 50 55 the first transmitting channel device, the second output of which is the output of the clock pulse generator and is connected to the clock input of all but the first transmitting channel devices, and the transmitting clock signal selector is inputted to each transmitting channel device other than the first one to the inputs of which the input and output of the clock pulse generator, the transmitting control unit, are connected, respectively, the first 275836 the interval of the duplicated inserts is ruets 1. Thus, the negative inserts entered on the transmitting side are eliminated and the first symbols of the sync signals are restored. The recovered pulse flow enters the corresponding system output. Invention Formula ten A system of asynchronous coupling of pulsed streams containing, on the transmitting side, k transmitting channel devices (where, 2, ...), each of which contains a driver pulses of 1X1X pulses, the input of which is the signal input of the corresponding transmitting channel device, each transmitting channel device, except the first one, contains a single device, the second and third outputs are connected respectively to The transmitting dynamic memory block, the first output of which is the output of the corresponding transmitting card, each transmitting device, except for the first one, contains one device, the second and third outputs are connected respectively to the first and second inputs of the temporary detector, and the output of the first prohibition block are connected to the first input of the transmitting dynamic memory block, and on the receiving side - k-1 (where k 1,2, ...) receive channel devices, each of which contains the receiving the dynamic memory unit, to the first input of which the output of the second inhibit unit is connected, the first output of the dynamic memory unit is connected to the first input of the phase locked loop (FALCH) unit, and the second output is the output of the corresponding channel receiving device, which differs from the fact that, in order to increase the reliability of the system, the signal input of the first transmitting channel device is connected to the first output 0 five the first transmitting channel device, the second output of which is the output of the clock pulse generator and is connected to the clock input of all but the first transmitting channel devices, and the transmitting selector of the clock signal is connected to each transmitting channel device except the first respectively, the input and output of the clock pulse generator, the transmitting control unit, the first 7 a frequency divider transmitting a controllable delay unit and a third prohibition unit, to the first input of which the third time detector input and clock inputs of the transmitting control unit, the first frequency divider and the transmitting clock selector, the first and second outputs of which are connected to the second input of the transmitting dynamic memory unit and the first signal input of the transmitting control unit, are connected to the second signal input the input of which is connected to the output of the first frequency divider, to the signal input of which the first output of the transmitting control unit is connected, the second output of which is connected to the second input of the reject block and the first input of the transmitting block of a controlled delay, to the second input of which is connected the first input of the first block of the ban, which is the clock input of the corresponding transmitting channel device, as well as to the third input of the transmitting block of the dynamic memory, the output of the third block of the ban, to the third input of which is connected to the first output of the temporary detector, the second output of which is connected to the second input of the first block of the ban, to the third input of which is connected the fourth input of the temporary of the detector and the output of the transmitting controllable delay unit, to the third input of which the fourth output of the transmitting dynamic memory unit is connected, L additional outputs of which are connected respectively to the L additional inputs of the transmitting controllable delay unit and the receiving selector is inserted into the receiving channel devices on the receiving side clock signal, the first signal and clock inputs of which are corresponding . ten 20 25 - 15 th 4275838 Each input, except for the first, receiving channel device, and the output is connected to the second input of the receiving dynamic memory block C the control receiver, the second and third frequency dividers, the controllable delay receiving unit and the fourth prohibition block, to the first input of which the first input of the controllable delay receiving unit is connected to the output of the PLL, to the second input of which the third output of the dynamic memory receiving unit is connected , to the third input of which is connected the second input of the fourth block of prohibition and the output of the receiving block of controlled delay, to the second input of which is connected the first output of the receiving control block, the second output of which is connected the first input of the prohibition unit, the second input of which is psdhl; the clock inputs of the second tre t of the frequency dividers, the psi control of the control receiving unit and the clock input of the receiving selector are synchronized15 30 35 40 45 la, to the second signal input of which the second signal e, v is connected. to the receiving control unit and} zjo, - the second frequency divider, to the third input of which the third is connected I output of control receiver, k the third input of which is connected;; the third divide. W htr, to the signal input of which is connected: -: the third output of the receiving unit at the NIN rarle, the other outputs of which are connected to the corresponding inputs of the close selector of the synchronizing signal. The output of which is connected to the fourth input of the receiving control unit, the fourth output of the receiving dynamic memory unit is connected to the third input of the receiving controllable delay unit, the L additional inputs of which are connected to the L additional outputs of the receiving dynamic memory block to allllish1ll1llllllllsthlg l iiuvum juuirum .llllllll g inf.sign. Sinhosienal Inu.Sign Sinh rsienal 0tr. Vault  Positive - on BcmaSKtt l .. Synchcienal . . Insert - OmpuLiam. dsto / a a .1ЛШ1Г1Ш1. L1L1LYASH1PL. SH1 Sh 1LSH1G1LLYAG JinJlJTJUlJLrLrmnr Faye. 2 inf. Synchsienal