SU604181A1 - Arrangement for simultaneous transmitting of analogue signal by delta-modulation technique and of binary signal of low-speed discrete information - Google Patents

Description

(54) DEVICE FOR SIMULTANEOUS TRANSMISSION

ANALOG SIGNAL BY DELTA MODULATION AND LOW-SPEED BINARY SIGNAL

DISCRETE INFORMATION. 1.2

In this case, the key output is connected to the second input of the OR element, and to the receiving side, a delta-demodulator, to the control input of which clock pulses are fed, and the output is the analog signal output, and the serially connected key and driver-binary IDI signal In this case, the signal input of the delta demodulator is connected to the first key input, and the IDN reference frequency pulses are fed to the control inputs of the key and the binary ID signal generator, and the serially connected analysis unit is input on the transmitting side and a correction unit, while the first inputs of the analysis and correction units are connected to the output of the divider modulator, the second inputs are connected to the second key input, the output to: which is connected to the third input of the analysis unit, while the first output of the correction unit is connected to the third input the prohibition element, and the second one is connected to the third input of the OR element; in addition, the correction unit is made in the form of prohibition and pulse insertion elements, the outputs of which are the first and second outputs of the correction unit, respectively, through memory blocks Connected to the inputs of the match element and to the first inputs of the inhibit and insertion of pulses, and the output of the coincidence element is connected to the control, inputs of the storage units, the second inputs of the inhibit and insertion elements are the first input of the correction unit, the third inputs are The second input of the correction unit and the third inputs of the storage units are respectively the third and fourth inputs of the correction unit.

FIG. 1 shows the structural electrical circuit of the proposed device; in fig. 2 - timing charts of signals, explaining the operation of the device.

A device for simultaneous transmission of an analog signal by the delta modulation method and a binary signal of low-friction discrete information (NDI) contains a serially connected delta modulator on the transmitting side, the inputs of which are fed with an analog signal and clock frequency pulses, and prohibition element 2, the output of which connected to the first input of the element OR 3, as well as the key 4, to the first input of which the binary signal of the NDI is fed, and the second inputs of the key 4 and of the Element 2 are impulses of the reference frequency of the NDI, while the output of klk) cha is connected to the second input of the element OR 3, and on the receiving side - a delta-demodulator 5, the control input of which has pulses of the clock frequency, and the output is the output of the analog signal, and the serially connected key 6 and driver 7 of the binary IDN signal: at the same time, the signal input of the delta-demodulator 5 is connected to the first input of the key 6, and to the control inputs. key 6 and driver 7 of the binary NDI signal, pulses of the reference frequency NDI, pulse communication path 8 are fed, on the ne (in the other side, serially connected analysis unit 9 is inserted into correction unit 10, the first inputs of analysis and correction unit 9 are connected to the output of the delta modulator 1, the second inputs are connected to the second input of key 4, the output of which is connected to the third input of block 9, while the first output of block 10 is connected to the third input of element 2, and the second is connected to the third input of the element OR 3, except addition, block 10 execute n in the form of prohibition elements P and insertion of 12 pulses, whose outputs, respectively, the first and second outputs of block 10, are connected via memory blocks 13, 4 to the inputs of the coincidence element 15 and to the first inputs of prohibition elements P and insertion of 12 pulses, and output element 15 is connected to the control inputs of the storage units 13, 14, while the second inputs of the inhibit elements 11 and the insertion of 12 pulses are the first input,: the third inputs are the second input 10, and the third inputs of the storage blocks 13, 14 are respectively third and fourth m inputs chunk0 correction.

The device works as follows. g The binary DM signal (Fig. 2a) with a clock frequency equal to the speed of symbol following in the pulse path 8 of the communication passes successively through the prohibition element 2, where pulses are prohibited at the clock points of the NDI, and the OR element 3, to the second input of which 0 Binary signal NDI (Fig. 2.6) with the duration of the characters generated by key 4 (Fig. 2c), controlled by IDN reference frequency pulses (Fig. 2g). From the output of the element OR 3, the resulting binary signal, which is an alternating pos. The length of the character of the NDI signal is n combinations of the symbols of the DM signal with allowance for the distortion correction. For this purpose, sequentially connected analysis units 9 and corrections 10 are used. A pulse is formed at the first output of block 9. sy (Fig. 2d), corresponding to the cycles when the DM signal is represented by a pause and the NDI signal by a pulse, and at the second output (Fig. 2e) - on the contrary, when the DM signal has a pulse, and the NDI signal - a pause. Pulse signals (Fig. 2e. E) are fed to block 10 to start, respectively, the storage blocks 13 and 14 (Fig. 2g, h), for example, triggers: The correction impulses corresponding to the inversion, which are impulses / pauses, are generated by the impulse prohibition element 1 mainly in those cycles when a pulse follows a pause in the DM signal, i.e., at the beginning of the bursts. This signal (Fig. 2) using the prohibition element 2 corrects the DM signal n resets the S5 memory unit 13. Similarly, the correction pulses corresponding to the pause / pulse inversion are formed by the pulse insertion element 12 mainly at the beginning of the pause packets. This signal (Fig. 2k) with the help of the element OR 3 corrects the result) of item 1 sig®nal and resets the storage unit 14.

It is possible that the tact of the proposed correction of the DM signal will coincide with the next clock signal HZIH. Then, with different symbols of the DM and IDN signals, both storage units 13 and 14 will be triggered. The pulse signal (Fig. 2L) from the element 15 will reset both storage units 13, 14, with no correction pulses at the inputs of prohibition elements 2 and OR 3 will be. If the symbols of the DM and IDN signals are the same, then due to the absence of pulses from the outputs of the analysis block 9, the correction of the DM signal is postponed until the clock where the DM signal has the symbol of the same type as the IDN signal, which necessitates correction. The binary signal (Fig. 2m) from the output of the inhibit element 2 is fed to one of the inputs of the OR element 3, from which the signal (Fig. 2 and) enters the pulse communication path 8. At the receiving side, the analog signal is generated as a result of demodulations the resulting signal, and the binary signal IDN by extracting the corresponding symbols from the same signal.

Claims (2)

Invention Formula A device for simultaneous transmission of an analog signal by the delta modulation method and a binary signal of low-speed discrete information (IDN), containing on the transmitting side serially connected delta modulator, to the inputs of which an analog signal and a clock frequency pulse are applied, and a prohibition element, the output of which connected to the first input of the OR element, as well as the key, on the first input of which an IDN binary signal is supplied, and the IDI reference frequency pulses are sent to the second inputs of the key and the prohibition element, while In this case, the output of the key is connected to the second input of the OR element, and on the receiving side a delta demodulator, to the control input of which the pulses are applied (w (n (frequency), and the output is the output of the aia-choc sync and serially connected key and Forming the binary IDN signal, the signal input of the delta-demodulator is connected to the first key input, and control IDC key inputs and the IDID binary signal generator are supplied with IDID reference frequency pulses, in that. In order to increase the accuracy of the analog curio transfer at a limited bandwidth of the pulsed communication path, serially connected analog block and correction block are entered on the transmitting side, the first inputs of the analysis and correction blocks are connected to the output of the delta modulator, the second inputs are connected to the second input of the key, the output of which is connected to the third input of the analysis unit, the first output of the correction block is connected to the third input of the prohibition element, and the second - connecting to the third input of the AND element I. 2. Flo device p. 1, characterized in that the correction block is made in the form of prohibition and pulse insertion elements, the outputs of which are the first and second outputs of the correction block 1, respectively, are connected to the inputs of the match element and the first inputs the elements of the prohibition and insertion of pulses, and the output of the element of coincidence is connected to the control inputs of the storage blocks, while the second inputs of the elements of the prohibition are inserted The 0 pulses are the first input of the correction unit, the third inputs are the second input of the correction unit, and the third inputs of the storage units are the third and fourth inputs of the reccorn block 5, respectively. Sources of information taken into account in the examination: . Ovchinnikov V.N. Discrete multichannel systems for entering information into digital computers, M., “Energie, 1968, p. 40-46.