SU1437977A1 - Extractor of clock pulses - Google Patents

Abstract

The invention relates to a pulse technique and can be used in digital transmission systems of data over a wired or fiber-optic channel. The purpose of the invention is to improve the reliability of the device by reducing the sampling rate when processing the input signal, which increases the transmission rate of the discrete signal by almost two times. signal. To do this, the third 8 and fourth 9 triggers and the shaper 7 short pulses are added to the device. In addition, the device contains triggers 1 and 2j pinu 3 clock pulses, elements AND-KE 4 and 5, input bus 6, output bus 10. on the carpet of its period, this is eliminated by opag. on the proximity of the fronts of the input signal of clock pulses, which eliminates the loss of information when it is received. The operation of the device is explained in timing diagrams 1-1, p & n & data in the specification. 2 Il.

Description

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11437977

The invention is designed for pulsed T inTHKG and can be used for E digital data transmission systems of wired or fiber optic channels and is intended to allocate a clock frequency when receiving Wlodtti Sirnzla in NRZ code or different types of linear codes of type 1B2B;

The purpose of the invention is to increase the reliability of operation by reducing the sampling rate when processing the input signal, which is equivalent to almost twice the rate of transmission of a discrete signal,

On Lig.1, an electrical structural diagram of the device is shown in FIG. 2, time diagrams of the diagram, in accordance with its operation.

The clock clock pulse splitter contains a pen 1 and second 2 triggers, the clock inputs of which are connected to the 3 clock 1-pulses 1 and K-inJ5

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At its outputs, the Resolution signal (FIG. 2 d) 3 according to which, at the next sync pulse from trigger code 1, trigger 9, a Shift signal (FIG. 2 g) 5 arrives at the second input of element 4 or 5, and the output phase is shifted signal fj at the output of the trigger 4, If the differentiated signal from the input of the imaging unit 7 coincides with the negative edge of the signal fJ allocated on the bus 10, then there is a danger of falsely recording the input signal to the subsequent stages of the decoder or regenerator.

With such a coincidence, the trigger 8 is transferred to the opposite state. The signal from the output of the trigger 8 is recorded in the trigger 9 with a frequency f. Elements 4 and 5 and trigger 2 shift the output signal f, by half of its period.

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dy of the second flip-flop 2 are connected to the highs-35 of the fronts of the input signal and at the output of the first 4 and second moves, respectively, of the NAND; the input goinl 6 is connected via the shaper 7 short pulses to the I and K inputs of the third trigger 8, the direct and the reverse outputs of which are connected respectively to the I and K inputs; the fourth trigger 9, the clock input of which is connected to the output the first one, trigger 1 and with the first input inputs of the first 4 and second 5 NAND elements,. the second inputs of which are connected respectively with the inverse of the outputs of the fourth trigger 9, the inverse of Hbs i the output of the second trigger 2 is connected to the TSKTCBbB-j input of the third trigger 8 n s: the output spike 10.

The device operates as follows.

From bus 3, the frequency of the dual frequency 2f (, (FIG. 2, a) is sent to the clock inputs of the trigger 1 and 2. The trigger 1 performs the functions of frequency divider two and produces sync clock 45

output clock signal, which eliminates the loss of information when it is received from

Claims (1)

Formula invented and The clock pulse selector containing the first trigger, the clock input of which is connected to the clock pulse bus and the clock input of the second trigger output of which is connected to the output bus, the I and K inputs of which are connected to the outputs of the first and second H-HEj elements of the first inputs, respectively. which are connected by the t output of the first flip-flop, and the input Šinud, which differs from the fact that in order to ensure the reliability of the operation, the third and fourth flip-flops and the short-termrrfatel of short pulses, the input of which is connected to input bus, output - with I- and K-inputs of the third trigger, the clock input of which is connected to the output bus., direct and a signal with a frequency f, (Fig.2 b), near the clock pulse selector, containing the first trigger, the clock input of which is connected to the clock pulse bus and with the clock input of the second trigger output of which is connected to the output bus, the I and K inputs of which are connected to the outputs of the first and second elements H-HEj, respectively, the first inputs. Which are connected by the t output of the first trigger, and the input switch differs in that in order to ensure the reliability of operation, the third and fourth triggers and the short termrtor of them are entered Olsen, whose input is connected to an input bus, the output - to I- and R-gi vhodag third flip-flop, a clock input connected to the output line, and straight. corresponding to the clock frequency of the input signal in the inverse outputs are connected to the corresponding fj (fig „2 s) under the condition fc.f. consequently, the I- and K-inputs of the fourth. The input signal from bus 6 (FIG. 2) is differentiated along the front with the aid of the imaging unit 7, (FIG. 2 g) and enters  a trigger whose clock input is connected to the first inputs of the first and second AND-NOT elements; second entrances  a trigger clock input of which is connected to the first inputs of the first and second AND-NOT elements; second entrance simultaneously on the I- and K-inputs of the trigger-55 which are connected respectively to ra 8 ,, synchronized with the signal frequency f “with bus 10, trigger 8 causes direct and inverse outputs of the fourth trigger. 0 five 0 At its outputs, the Resolution signal (FIG. 2 d) 3 according to which, at the next sync pulse from trigger code 1, trigger 9, a Shift signal (FIG. 2 g) 5 arrives at the second input of element 4 or 5, and the output phase is shifted signal fj at the output of the trigger 4, If the differentiated signal from the input of the imaging unit 7 coincides with the negative edge of the signal fJ allocated on the bus 10, then there is a danger of falsely recording the input signal to the subsequent stages of the decoder or regenerator. With such a coincidence, the trigger 8 is transferred to the opposite state. The signal from the output of the trigger 8 is recorded in the trigger 9 with a frequency f. Elements 4 and 5 and trigger 2 shift the output signal f, by half its period. fronts of the input signal and high- output clock signal, which eliminates the loss of information when it is received from Formula invented and The clock pulse selector containing the first trigger, the clock input of which is connected to the clock pulse bus and the clock input of the second trigger output of which is connected to the output bus, the I and K inputs of which are connected to the outputs of the first and second H-HEj elements of the first inputs respectively. which are connected by the t output of the first flip-flop, and the input Šinud, which differs from the fact that in order to ensure the reliability of the operation, the third and fourth flip-flops and the short-termrrfatel are entered into it input bus, output - with I- and K-inputs of the third trigger, the clock input of which is connected to the output bus., direct and inverse outputs are connected respectively to. I- and K-inputs of the fourth inverse outputs are connected respectively to. I- and K-inputs of the fourth  a triggerJ whose clock input is connected to the first inputs of the first and second AND-NOT elements; second entrances which are connected respectively with direct and inverse outputs of the fourth, the same trigger. 6 e d Phie.g