SU1056489A1 - Device for majority sampling from asynchronous signals - Google Patents

Abstract

INSTITUTION FOR MAJORITY SELECTION OF ASYNGONAL SIGNALS, containing three RS-flip-flops, in which the single outputs are connected to the first, second, third inputs of the majority element, and the single installation inputs are the device inputs, the first AND element, the OR element and the first delay element, input which is connected to the output bus of the device, and the output to the zero setup inputs of the RS flip-flops, is deprived of the fact that, with the device’s reliability, it contains the second element I and the second element holders, the first, second and third inputs of the first element And are connected respectively to the single outputs of the first, second and third RS-flip-flops, the outputs of the first and second elements And are connected respectively to the first and second inputs of the OR element, the output of the majority element through the second delay element to the first input of the second element I, the second input of which is connected to the output of the first element of the rear axis of the axis, and the input of the element OR (L is connected to the output bus of the device. SP 65 4 ;;). 00 co.

Description

. This is true of automation (automation and automation technology) and can be used in digital multi-channel systems of security and reliability.

A device for majority 5 is known.

signal selection, containing six triggers connected via AND, OR-NOT with delay elements (1 The disadvantage of this device is significant complexity and low reliability, due to the presence of six triggers and a large number of communication buses in it.

H: The most closely related technical solution to the invention is a device for the majority selection of asynchronous signals, containing tS three RS-flip-flops that have single ones. the outputs are connected respectively to the first, second and third inputs of the majority element No, the element I, the first input of which is connected to the output of the majority element, and the output - to the output 20 of the device and to the output of the zadarhysi element, the output of which is connected to the zero inputs of the RS flip-flops and the OR element, the inputs of which are connected respectively to the single inputs of the first, second and third 25 RS-flip-flop, 6l ush imis device inputs. va, and output with the second input of element I. {2.

However, this device has a low reliability, in particular, the use of this device in multichannel channels with high speed and transmission of information signals on other communication lines simultaneously with synchronized signals will lead to a significant reduction in the reliability of the entire system as a whole. to the delay of one of the channels relative to the others, the processing of information signals in the system will be carried out using information from only two channels, without waiting for the arrival of information onnyh third signals kanala.40

Shl izob {shadows - povplenie reliability, in particular, by organizing the wait. the arrival of the input pulse from the 11th signal, which has the greatest delay. .

This goal is achieved due to the fact that a device containing three N8-triggers, in which one & 1 output are connected. respectively, with the first second and third inputs of the majority element, and the single setup inputs are the inputs of the device, the first AND element, the OR element and the first delay element, whose input is connected to the output bus of the device, and the output with zero installation inputs RS-triggers, contains the second element And the second 55 delay element, with the first, second and. the third inputs of the first element And are connected respectively to the single outputs of the first, second and third RS-flip-flops, the outputs of the first and second elements AND are connected respectively to the first and second inputs of the OR element, the output of the main element through the second delay element connect to the first input of the second element And, the second input of which is connected with the output of the first delay element, and the output of the element: OR is connected to the output power supply of the device ..

FIG. 1 shows the functional scheme of the device for the majority selection of asynchronous signals; in fig. 2 and 3 are timing diagrams for the operation of the device.

The device contains RS-triggers 1-3, majority element 4, elements AND 5 and 6, element OR 7, delay elements 8 and 9, input buses 10-12 pulse signals AND output bus 13.

Timing diagrams of the device operation are shown in FIG. 2 and 3, 1; de marked: the signals at the outputs of the corresponding. Elements of the device 1-9, the signals on the input buses 10-12. ustrshstva; signal to the output of your device 13; the maximum possible for this system, Cp ,, / desynchronization between the input lines, the required duration C of the output pulses on the bus 13.

The device works as follows.

Input signals from buses 10-12 are asynchronous. Consider a few cases prnema asynchronous signals. FIG. 2 signals to the inputs 10–12 of the device arrive at the same time, and the time of dissynchronization between the red and the last incoming signals does not exceed 1

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Upon arrival of the signal at input 10, trigger 1 is set to one and a single potential from the output of this trigger is applied to the first inputs of the majestic element 4 and element 5. At the outputs of these elements, zero potential values are saved. Upon arrival of the signal at input II, trigger 2 is set to one and a single potential from the output of this trigger is applied to the second inputs of the major element 4 and AND 5, resulting in a single potential being applied to the output of the major element 4, which is applied to the input of the delay element 9, and the output of the element And 5 remains zero potential. After the delay time of element 9, equal to the potccmoM output of element 9, the pulse, the duration of which is chosen equal to fgbix 13, goes to the first input of the element AND 6. At the npmiony signal ira input 12, it is set to 1grg 3, the potential from the c output which is applied to the third inputs of the major element 4 and the element AND 5, resulting in the output of the element TL 5 there is a unit potential, which is the four OR element 7 applied to the output bus of the device 13 and to the input element of the delay 8. After the time ki equal to the pulse tg, required for lieHbHOCTH JBbtxoworo, SIR, from the output of element 8, goes to the zero setting inputs of RS flip-flops 1-3, setting them in the outgoing state, thus terminating the formation of the output signal, to the second input of the element And b . The output pulse of the delay element 8 is selected based on the condition BfeixS for race max and the passage is blocked for the duration of this pulse (it burned delay 9 from the output of element 6 through element 6 to the input of element 7 OR; Thus, for the case when signals The inputs 10–12 of the device are received non-one-time. At the time, with out-of-sync, the first and last incoming signals that do not exceed the current device bus are generated by; the last input signal travels. In Fig. 3, the signals to inputs 10 and 11 go mortar t non-simultaneous with the desync time less than tl., the signal at input 12 is absent (due to failure or failure of the signal source). Similarly to the described case, the arrival of the second input pulse triggers delay element 9, the output pulse of which is fed to the input element And b Due to the absence of an input pulse on bus 12, the RS-flip-flop 3 remains in the zero state, therefore the output of the AND element also saved the raiTCK: zero, and the output of the delay elements is 8 unit. As a result, the pulse from the output of the delay element 9 goes through the elements AND b and OR 7 to the output bus of the device and the input of the delay element 8. After the delay time of the element 8 equal to fg, the signal from the output of element 8 goes to the zero setting inputs RS- Triggers 1–3, set the triggers 1 and 2 to the initial state and to the second input of the element A and b, stopping the formation of the output pulse in bus 13, i.e., in the absence of a signal on the input bus 12, the output pulse fpr Qrprytc after Tpg (.f, after P {N1 input input signal on the cable 11. So Thus, in the device, during the time fpa, y, Q after the arrival of the second of the input signals, the third input signal is organized. In case the third signal arrives, during the waiting time, then at the front of this signal, the formation of a signal at the output It is 13. If the signal is not received during the waiting time, a pulse on the output bus of the device is formed — at the end of the time the days are open. In addition, the device has a high speed, i.e. the formation of the output signal on bus 13 starts at the moment of the leading edge of the last of the asynchronous input signals. Thus, the device for the majority selection of asynchronous signals has increased reliability by simplifying the design of the device and the ability to use it in high-speed systems with parallel, transparent transmission of information and synchronized funds.

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Claims (1)

DEVICE FOR MAJORITY SELECTION OF ASYNCHRONOUS SIGNALS, containing 1 or 3 RS-flip-flops, in which unit outputs are connected respectively to the first, second and third inputs of the majority element, and unit installation inputs are device inputs, the first AND element, the OR element, and the first delay element, whose input connected to the output bus ustroyst- wa, and output - with zero installation vho- 'rows RS- trigger ,, by Leach in that, to improve the reliability Device ^for: roystva, it includes a second aND gate and a second butt member rzhki, and the first, second and third inputs of the first element And are connected respectively to the unit outputs of the first, second and third RS-triggers, the outputs of the first and second elements And are connected respectively to the first and second inputs of the OR element, the output of the majority element through the second delay element is connected to the first input of the second AND element, the second input of which is connected to the output of the first delay element, and the output of the OR element is connected to the output bus of the device. "1056489 2