SU1434558A1 - Digital signal regenerator - Google Patents

Abstract

The invention relates to telecommunications technology and can be used in digital transmission systems. The purpose of the invention is to improve the noise immunity of the regenerator. The regenerator contains a correction amplifier 1 with AGC, a clock synchronization unit 2, a coincidence unit 3 (BS), an output signal shaper 8. The goal is achieved by introducing into the device an extension of pulses (RI) 4, delay lines: (LZ) 5, RS flip-flop 6 and BS 7. RI 4 expands the pulses by an amount at least 2 times higher than the phase tremors, i.e. The device completely eliminates the possibility of skipping information pulses due to phase jitter of clock pulses. On the BS 7 expr, rectangular pulses with the duration and magnitude of the phase jitter will appear, not exceeding the duration and magnitude of the phase jitter of the clock pulses. At the output of the output signal generator 8, the square-wave pulses have the same jitter of the front and rear edges, not exceeding the magnitude of the jitter phase of the gating pulses, 2 Il. i SP

Description

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The invention relates to Electro-communication technology and 8 digital transmission systems can be used.

The purpose of the invention is to increase the noise immunity of the regenerator.

Fig. F represents the structure; 1 | 1a electrical circuit of the proposed regenerator | in fig. 2 diagrams of assignments on his work. i The digital signal regenerator contains a correction amplifier 1 with 1 automatic gain control (fARU), a clock synchronization unit 2, a Lerve coincidence unit 3, a 4 pulse expander, a delay line 3 jS-trigger 65, a second coincidence unit 7, an output signal conditioner 8.

 The regenerator works as follows.

I Input digital information |; Ignsh from the output of the corrective amplification | 1body 1 with automatic gain control (AGC) (Fig. 3a) is supplied | to the input of the unit 2 clock synchronization and to the input of the first unit 3 to the | | From the output of the block 2, clock pulse synchronization (Fig. 3b) is fed to the input of the expander 4, which expands them by an amount at least twice the magnitude of the phase jitter (Fig. 36c). The extended pulses (Fig, 3p) feed p to another input of the first block of 3 Coincidence; now they register without error also those pulses that do not exceed the threshold at the moments when short gating pulses (due to phase jitter) deviate from their optimum positions (Fig. 3a), i.e. in this case, the possibility of missing information pulses due to phase jitter of clock pulses is completely excluded. However (Fig. 3a), the width and the possible temporal position of the output pulses of the first coincidence unit 3 (Fig. 3a, d), i.e. the jitter of pulses from the output of the first block 3 coincidence is greater than the jitter of clock pulses (Fig. 36, d). The pulses from the output of the first block 3 of coincidence are fed to the S input of the RS-flip-Tger and transfer it to the single state. The output signal of the RS flip-flop 6 is fed to the input of the block ry block 7, to another

the input of which receives gating short pulses (Fig. Ze) from the output of the block 2 clock synchronization, delayed by line 5 of the delay by an amount equal to about half the duration of the clock interval. In this case, at the output of the second block 7, rectangular

0 pulses of the duration and magnitude of the phase jitter, not exceeding the duration and magnitude of the phase jitter of the clock pulses (Fig. 36, i). These pulses are then fed to the input 5 of the globalizer 8 output signal and to the R input of the RS flip-flop 6, which is then returned to the initial (zero) state. At the output of the RS flip-flop 6, rectangular impulses (FIG. 3D) appear, the jitter of the leading edges of which is greater than the tremor of the leading edges, and at the output of the output signal generator 8, the square-wave pulses (FIG. 3C) have the same

5 phase jitter of the front and rear edges, not exceeding the magnitude of the jitter phase of the gating pulses.

Claims (1)

J -. 0 Formula from. bratis A digital signal regenerator containing a correction amplifier with automatic gain control (AGC), the output of which is connected to the input of a clock synchronization unit and the first input of the first coincidence unit, and an output signal generator, the output of which is the output of the regenerator, whose input is AGC, characterized in that, in order to improve the noise immunity of the regenerator, a pulse expander, delay lines and a series-connected RS flip-flop and a second block are introduced ovpadeni, a second input and whose output is connected respectively to the output of the delay line to which the input is connected 0 is the output of the clock synchronization unit, and with the input of the output signal generator, while the output of the clock synchronization unit is connected to the second input through the pulse expander 5 of the first match block, the output of which is connected to the S-input of the RS flip-flop, the R-input of which is connected to the output of the second match block. five 0 five but g l Fie.2