SU1211758A1 - Device for determining parameter of power model of average value of random signal - Google Patents

Abstract

The invention relates to specialized computer aids. The aim of the invention is to improve accuracy. The goal is achieved by introducing an adder, a dividing unit, a counter, a permanent memory unit, and a clock generator into the device. 1 il.

Description

The invention relates to specialized computer aids for determining a model parameter of an average value of a random signal.

The aim of the invention is to improve the accuracy.

The drawing shows a block diagram of the device.

The device circuit consists of a clock pulse generator 1, a comparison circuit 2, a receiver register 3, a generator of power function 4, auxiliary register 5, first and second adders .6 and 7, and a division unit 8. The generator, a power function consists of a counter and a block this memory.

The device on an arbitrary ik-m, function change interval works as follows.

If a sequential discrete digital array XO) is supplied to the input of the device, it is an additive mixture of the function of mean m (1) and noise (interference) x li), i.e.

x (0 mx (i) + x (i),

and it is known a priori that x (j) is a normal random process with an equal zero expectation, satisfying the condition

1: x (,

-am (i) allows representation by a power model

. t) ((P,

where l is an indefinite parameter of the function

meanings; ps - known, given by the view

models, parameters, then taking into account expressions (2) and (3), the parameter can be found from the condition. N

2: {x {iv “.; -ci 0 or

N

. (4) where did u come from.

)-with

about

14

f. "

2-1

iri The device works in

algorithm (4).

in the initial state (rfe-interval) in registers 3 and 5 there are codes corresponding to

K-1 g - K-1 „

; p1- - On command from the pulse generator, the code of the second information x (arrives at the comparison circuit 2, the output of which forms the code x {ik) -c,

received by the adder 6 on the first input, to the second input of which register $ 1 and 3 receives the code tL r -,

(i} -cJ.

14

At the output of the adder 6 fb p peace

ts

the sum

.ElxOl-c,

which is entered

0

to the receiving register 3 and simultaneously to the first input of the division unit 8.

0 At the same time, from the power function generator 4, the value is fed to the first input of the adder 7, to the second input of which from the additional register 5 is fed the sum.

5s

The result of the summation determined by

.the value of L-, p is recorded in d-g 1,

An additional register 5 and at the same time is fed to the second input of the division unit 8. At the output of the division unit 8, the value of the parameter v is formed, corresponding to the expression (4) for the interval 1 «k k.

.

For the interval i i (k + i), i (k + g) ... N, the operation of the device is completely analogous to that described, J

Claims (1)

Invention Formula five 0 A device for determining a parameter of a power model of an average value of a random signal containing registers, a comparison unit, the first input of which is an input of setting a device threshold, whose information input is connected to the second input of a comparison unit, characterized in that, in order to increase the accuracy, it is entered adders, dividing unit, counter, permanent memory unit, clock generator, clock inputs of registers, adders, comparator block, dividing unit and counting counter input are combined and connected to course of the clock output of the comparison unit is connected 3121 with the first input of the first adder, the second input of which is connected to the output of the first register, informational. the input of which is combined with the first information input of the division unit and connected to the output of the first adder, the second information input of the division unit is combined with the information input of the second register and connected to With X / iV / 7584 the output of the second adder, the first and second information inputs of which are connected respectively to the outputs of the permanent memory unit and the second J register, the output of the counter is connected to the address inputs of the permanent memory unit, the output of the division; the output is the output of the device.