SU961150A1 - Pulse recurrence rate amplifier - Google Patents

Description

one

The invention relates to a measurement technique and can be used in digital measurement instruments and digital automatic control systems for scaling information presented in a frequency-pulse form.

A pulse frequency multiplier is known, comprising a reference frequency generator, a frequency divider, a counter, a comparison unit, a group of controlled shift registers, and an OR element tl.

The disadvantages of this multiplier are the complexity and low noise immunity.

The closest to the invention according to the technical essence of VLT, is a pulse multiplying frequency multiplier containing a reference oscillator, a frequency divider and bitwise connected to a comparison unit, a pulse counter and a reversible counter, the AND element, the trigger and the key, the first input of which

connected to the output of the reference generator, and the output - to the input of the pulse counter, the input bus is connected to the first inputs of the frequency divider, the And element and the trigger, the second input of which is connected to the output of the frequency divider, the output to the second input of the key, with the second input elements , and with the addition input of the reversible counter, the input of which is subtracted is connected to the output of the element I, and the output of the comparison device is connected to the reset input of the pulse counter and to the second input of frequency divider 2.

The disadvantages of the known device are low noise immunity and complexity.

The purpose of the invention is to improve noise immunity while simplifying the device.

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Claims (2)

To achieve the goal, the pulse multiplier, containing the frequency generator, two shift registers and a frequency divider, whose input is connected to the clock input of the first register, a delay element, the output of which is connected to the sync input of the first shift register, and input - with the output of the frequency divider, the input of which is connected to the output of the reference frequency generator, and the clocking input of the second shift register, the counting input of which is connected to the input bus, and the information outputs to informational inputs of the first shift register. The drawing shows the structure of the proposed multiplier. The device contains a reference frequency generator 1, registers 2 and 3 shift ha, frequency divider k, support element 5. The multiplier works as follows. The pulses of the reference frequency f from the output of the generator 1 are fed to the clock input of the register 2 and to the input of the divider k, the division factor of which is equal to the given multiplier factor H, the pulses of the divider, the frequency of which is equal to fn / M, are fed to the clock input of the register 3 and through element 5 register synchronization 2. Each multiply-frequency pulse arriving at the counting input of register 3 is recorded in the first bit of this register (the bit from O is transferred to state 1) and is sequentially transferred at a speed corresponding to stvuyuschey frequency of the control pulses / M, generated at the output of divider k. In addition, the pulses arrive at the input of the delay element 5. Each time the pulse from the output of the delay element 5, supplied to the synchronous input of register 2, both marks the rewriting of the contents of register 3 into register 2. The values of the frequencies fQ and fg / M, as well as the number of bits of the registers 2 and 3 of the shift, are chosen so that the period of the clock frequency f / M was carried out by a single survey of each bit of register 2 (a sequential shift of all bits to the older ones). The frequency of the pulse sequence at the output of device 4 is proportional to the code Nj written in register 3. For F, we have c - f –J Bb / x where n is the number of bits of shift register 3. The value of the code MC formed in the registrar 3 is equal to MTizm (, where is the measuring interval. The measuring interval in the proposed device is determined by the number of bits n of the shift registers and the clock frequency period о / М Тизм iM / fQ. Taking into account expressions (2) and (3) rewrite formula (1) in the form of IEM -I g (t) at. (4) meas From the analysis of the last expression it follows that PgLi.- generated by the device is proportional to the average value of the multiplied (input) frequency F- over the measuring interval Unlike traditional principles of frequency multiplier, lasers encode by multiplication frequency period Gu., the proposed device uses the method of direct pulse counting for the measuring interval} The value of the Nj code, formed in register 3, is an integral estimate of the input frequency of the RIO, which guarantees high noise immunity of the proposed device. 8 The proposed frequency multiplier the pulse sequence multiplication factor is determined only by the division factor of the divider and does not depend on the input signal. 59 The proposed device has a logical simplicity of construction, since there are no reset operations and synchronization problems, a highly stable multiplication factor, independent of both the jitter of the multiplied frequency pulses and the impulse noise. Introducing a delay element and new connections into the device simplifies it and reduces output ripple, which allows the invention to be used to multiply non-uniformly following pulse sequences. The claims of the Pulse Frequency Pulse Cutter, comprising a reference frequency generator, two shift registers and a shift frequency divider 6, characterized in that, for the purpose. increase noise immunity while simplifying the device, a delay element is inserted in it, the output of which is connected to the synchronous input of the first shift register, and the input to the output of a frequency divider whose input is connected to the output of the reference frequency generator, and a clock input of the second shift register whose counter input is connected with the input bus, and information outputs - with the information inputs of the first shift register. Sources of information taken into account during the examination 1. USSR author's certificate ff 58063t, cl. H 03 K 5/156, 1976. 2. USSR author's certificate №, cl. H 03 K 23/00, 1975. / L / jr