SU705506A1 - Device for display of digital data - Google Patents

Description

(54) DEVICE FOR REPRODUCING DIGITAL INFORMATION

with the output of the third threshold circuit on one of the outputs of the three-bit pulse counter, the output of the second OR circuit is connected to the counting input of the three-bit pulse counter, the output of the fourth OR circuit is connected to the zero setting input of the three-bit pulse counter, and the output of the third OR circuit It is connected with one of the trigger inputs, the second input of which is connected to the output of the fifth OR circuit and to the synchronization bus, the inputs of the fifth circuit OR are connected to the outputs of the three-digit pulse counter, one directly, and the second through the delay, the output of the second flip-flop through the pulse shaper is connected to the n "formational bus.

FIG. 1 shows the structural scheme of the described device; in fig. 2 is a timing diagram of its operation: A device for reproducing digital information comprises a serially connected reproducing magnetic head 1, an amplifier 2, an amplitude pg-. reaper 3 and the first pulse shaper 4 (Fig. 1). The output of the amplitude limiter 3 is connected to the integrator 5 input, and the integrator 6 to the inverse output. Integrator 5 and 6 are integrated into the output of the first pulse generator 4, and their outputs are combined with the first OR circuit 7. The output of the first circuit OR 7 is connected in parallel with the threshold schemes: at the level of 0.17 of the maximum amplitude of the integrated signal - the first threshold scheme 8; at the level of 0.5 - the second threshold scheme 9; at a level of 0.83 - a third threshold circuit 10. The outputs of the threshold circuits 8, 9, 10 are combined by the second circuit OR 11, and the outputs of the threshold circuits 9, 10 are combined by the third circuit OR 12. To start the third threshold circuit 10 pEDiRy connected in series with one input fourth circuit OR 13 AND zero setting input three-digit counter pulse pulse 14. The counting input is three times; A pulse counter 14 is connected to the output of the second OR II circuit, and a third bit single output is connected to another input of the fourth OR circuit 13. The second output unit of the third discharge of the three-digit pulse counter 14 is connected in series with a delay block 15 and one input A circuit OR 16, the other input of which is connected to the single output of the first discharge of the three-bit pulse counter 14, and the output to the synchronization bus. In addition, the output of the fifth circuit OR 16 is connected by a single input trigger 17, the zero input of which is connected to the output of the second circuit OR 12. A second pulse generator 18 is connected to the single output of the trigger 17,

the output of which is connected to the information device.

Reproduced by reproducing magnetic head 1, the signal after amplification of amplitude and phase-frequency corrections in amplifier 2 and hard, inertialess amplitude limits using amplitude limiter 3 takes the form shown in the ultrasound diagrams V / (Fig. 2). The signal structure Vj contains three time intervals between adjacent, zero-intersections, related to each other as 1: 2: 3. At the same time, the maximum interval has a duration equal to 2Tt (where Tt is the duration of a cycle) and corresponds to the combination. 00 input information of the tsirnno binary sequence.

Ultrasonic and V} signals, taken respectively from the direct and inverse outputs of amplitude multiplier 3, are integrated with the help of integrators 5 and 6. The integrators discharge into the zero state (are discharged) by each zero-intersection pulse V produced by the first one. pulse 4. In order to ensure the linearity of the output voltages Vg and Ve of the integrators 5 and 6, the integration time constant is chosen to be longer than the duration of the cycle - TT. The voltages Vj and V are summed. With the help of the first circuit, OR 7, and are fed to the threshold circuits 8, 9, 10. At the output of the first threshold circuit 8, the output of the input is integrated.

Signal V / Reaches a value of 0.17

bt its maximum amplitude. Similar ito, at the outputs of the second and third threshold

Circuits 5 and III appear pulses, krgda

5, the signal level Vr is 0.5 and 0.83, respectively, of its maximum amplitude. The pulses taken from the outputs of the three threshold circuits 8, 9, 10 are mixed on the second

Or 1 G scheme, as a result of which a sequence of pulses Vn is formed with a period PM of the following, equal to 2Tt / 3. The pulses taken from the outputs of the second and third Threshold Schemes 9 and 10 are separately cMenjH on the third scheme OR 12, as a result of which the information sequence $ Zero of the zeros Ytz is generated. However, the T1d sequence is unequal in time. Its temporal alignment is performed with the help of taq sync pulses, which are generated as follows.

The pulse sequence Un is fed to the counting input of the three-digit pulse counter 14, where it is divided into three according to the frequency of the follow- ing. The three-bit pulse counter 14 is reset to its original state.

Claims (3)

. the zero state as pulses Y | p, taken from the output of the third threshold circuit 10 (corresponding to the 00 combinations of the input information binary sequence), hook and pulses, taken from the unit output of the third discharge of a three-bit pulse counter .14. In this way; from the single output of the first discharge of the three-discharge pulses 14, the sequence and c | pulses of V are removed, and the single output of the second discharge of the sequential pulses of V. The sequence of pulses of V is delayed by a time equal to Tt / 3 using the delay block 15 and mixed with the pulses Vi4 on the fifth OR circuit 16. The sequence of Vie pulses, taken from the output of the OR circuit 16, is you; hard clock clock sequence. The Vie clock pulses set the trigger 17 and the one state, and at the Beort state, the trigger is flung with each Vtt pulse. The equalized output information sequence of zero zeros Vij is generated from the positive fronts of the voltage Vif, taken off from the single output of the trigger 17c using the second pulse shaper 18. The presence of integrators in the device allows it to reliably protect it from the effects of additive high-frequency interference. In this case, high-frequency interference does not occur on the device's output busses, either via the information channel or the synchronizing channel. ; DETAILED DESCRIPTION OF THE INVENTION A device for reproducing digital information, comprising a sequentially reproducing Magnetic Head, an amplifier, an amplitude limiter and a first pulse shaper, as well as a trigger, a three-bit pulse counter, a delay unit, and output BUSES that have; to increase noise immunity, the device is equipped with the first OR circuit, two inputs of which are connected via integrators to the corresponding outputs of the amplitude limiter, whose input is connected via an amplifier to a reproducing magnetic head, and the outputs are connected to the input of the first pulse generator, the output of which is connected simultaneously to the second inputs of the integrators, and the output of the first OR circuit is simultaneously connected to the inputs of the three threshold circuits, and the inputs of the second OR circuit are connected to the outputs of all three threshold circuits and the inputs of the third OR circuit are connected respectively to the outputs of the second and third threshold circuits, and the inputs of the fourth OR circuit are connected to the output of the third threshold circuit and one of the outputs of a three-bit pulse counter, and the output of the second OR circuit is connected to the counting input of a three-bit pulse counter, .the output of the fourth circuit OR is connected with the zero setup input of the three-bit pulse counter, and the output of the third circuit OR is connected with one of the inputs of the trigger, the second input of which is connected to the output of the fifth circuit OR and to the bus synchronization, the inputs of the fifth circuit OR are connected with the outputs of a three-bit pulse counter, one is directly, and the second is through a delay unit, and the trigger output is connected to the information gateway through the second pulse generator. Sources of information taken into account in the examination 1. US Patent No. 3226685, Kji. 340-172.5, published. 1965. 2. US patent number 3377583, cl. 340-174.1, publ. 1% 8. 3. US patent number 3357003, cl. 340-174L, published. 1967 (prototype). VKfOfHOMT tHiHui ttaei 17