SU1218503A1 - Device for majority sampling of asynchronous signals - Google Patents

Abstract

The invention relates to automation and computing and can be used in digital multi-channel systems of increased reliability. The purpose of the invention is to increase the reliability and simplification of the device. The device solves the task of receiving three pulses of asynchronous non-overlapping time pulses, which can be separated by a certain acceptable discrepancy time (rlc-max-). At the output, one pulse is generated at a clock frequency, and its occurrence is due to the reception of pulses less than two entrances. The lack of pulse reception on one of the inputs is marked on the corresponding additional output. The device contains triggers (D-triggers) 1-3, majority element 4, element AND 5, Pulse counter 6, element OR 7. Shaper 8 single "multiples, element NOT 9, elements AND 10-12. Asynchronous pulses from three sources are supplied to the information inputs 13-15 of the device. The reset bus is used to reset the triggers, and the 17-clock bus serves to synchronize the device. At the main output 18 of the device, an output signal is generated, and at the additional outputs 19-21, control information. The introduction of these features makes it possible to solve the problem with simpler and more reliable means. 3 il. (L from Is9 00 ate about 00

Description

one

The invention relates to automation and computing and can be used in digital multichannel systems of increased reliability.

The purpose of the invention is to increase the reliability and simplify the device.

1 shows a functional diagram of the device; FIG. 2 is a timing diagram of its operation for the case of receiving three pulses; in FIG. 3 - the same for the case of receiving two pulses.

The device contains triggers 1-3, the majority element 4, the element And 5, the counter 6 pulses, the element OR NOT 7, the driver of the single pulses 8, the element NOT 9, the elements And 10-12. In addition, the diagram denotes information inputs 13-15 of the device, the reset bus 16, the bus 17 clock pulses, the output 18 of the device, the control outputs 19-21 of the device,

As triggers 1-3 D-triggers are used. The information inputs 13–15 of the device receive impulses to be processed, which may not overlap each other in time and diverge I among themselves for the maximum for the Grass time,

An output pulse is generated at the output 18, synchronized with the pulses fed to the bus 17. clock pulses, if at least two pulses have arrived at the input At the control outputs 19–21, pulses appear in the event that the reception of a pulse did not occur at the corresponding information input 13–15.

The device works as follows.

By a signal on the reset bus 16, all the triggers 1–3 are reset (zero). The majority element 4, receiving the signals of logical zeros at the inputs, forms a logical unit at its output that keeps the pulse counter 6 in the zero state, not allowing it to produce a count of clock pulses received from the bus 17 Input signals arriving at information inputs 13-15 The principle is asynchronous. Therefore, for example, the reception and processing of pulses are considered in the following two characteristic cases: signals to

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Inputs 13-15 appear compactly with an interval from the first to the last pulse no more than .. max. i., one of the pulses is delayed by.

time more than 1-ro.os; mo.cs.Let the first impulse (FIG. 2) come to the information input 13 of the device. With this pulse, trigger 1 is transferred to a single state,

as a result, a logical unit appears at one of the inputs of the major element and element 5. However, the output signals of these elements are still unchanged. With the arrival of the second pulse at the information input 14, trigger 2 is transferred to the single state, as a result of which the majority element 4 is triggered and its LO LO code changes to zero on its code, which allows the pulse counter 6 to start counting the clock pulses from the bus 17. Capacitance the counter corresponds to the discrepancy time tpacc-Mwo- In this case, the counter does not have time to count to the last digit, since the third pulse (at information input 15) comes before the expiration of the specified time.

In this case, the trigger 3 is also set to a single state, and a single signal from its direct output is fed to the third inputs of the major element 4 and the element

AND 5, At the output of element 5, a signal of a logical unit appears, which is then inverted by the element OR NOT 7 and fed to the control input of the single pulse generator 8. At the arrival of the next bus clock 17, a positive pulse of duration equal to the period clock pulse

on the bus 17. It enters the output bus 18, the input element NO 9 and the first inputs of the elements 10-12, which are closed on the second inputs with zero signals from the inverse outputs D of the triggers 1-3. From the output of the element NO 9, a negative pulse arrives at the C inputs of the D triggers 1-3, and at the end of this pulse, the triggers return to the initial (zero) state. With

This output of the majority element 4 will be a single potential that resets to the initial state

pulse counter 6. The device returns to its original state and is ready to receive the next input signals.

Thus, for the case when signals to information inputs 13-15 of the device arrive non-simultaneously, but with a desynchronization time between the first and last incoming signals not exceeding Lpacc.MivKc the signal at the output 18 of the device is formed synchronously with the first clock pulse on the bus 17 after the last (third) input signal.

FIG. 3 shows a case when information inputs 13 and 14 are received non-simultaneously with a desynchronization time less

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pacc. "th 3 signal at information input 15 is absent altogether (due to a failure or failure of the signal source). At the same time, similarly to that described, the arrival of the second input signal causes the pulse counter to count clock pulses. / s from bus 17 and through time 1ra.ss; ma with. at its output, a signal of a logical unit appears, which is supplied to the second input of the STI-NOT element (FIGS. 2-6), which after | 1t-inverting by the OR-NOT element .7 is fed to the control input of pulses 8. The latter is synchronized with sequential clock pulse on the bus 17 generates a positive pulse (Fig.3-8), which is fed to output 18,: to the input of the element is NOT 9 and n the first inputs of the elements And 10-12, and so the element And 12 is open on the second input to single potential with the inverse output of the D-flip-flop 3, then this pulse passes to the output bus 21 (Fig.3-12), the signal Error about the third channel failure. From the output of the HE element 9, a negative impulse goes to the C inputs of the D flip-flops 1-3. At the end of this pulse, both triggers — and, therefore, the entire circuit — return to their initial state, and the device is ready to receive the next asynchronous signals.

Thus, waiting for the third input signal is organized in the device during the time calculated by the arrival of the second of the input signals by simple and reliable means. In case the third sig2185034

the cash comes while idle

After the arrival of the next clock pulse after the arrival of the leading edge of this signal, the output signal at output 18 is generated, tied in time to the clock pulses on bus 17. If the signal is not received during the waiting time, a pulse at the output 18 of the device is formed at the end of the waiting time. . In this case, one of the control outputs 19–21 generates a signal signaling the failure of the corresponding source.

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Claims (1)

Invention Formula The device for the majority selection of asynchronous signals, containing three flip-flops, S-inputs of which are the information inputs of the device, and the direct outputs are connected to the corresponding input of the major element, the element NOT, the reset bus, the clock bus, the first, second, and third elements connected to the corresponding control outputs of the device, and the fourth element AND, the output connected to one of the inputs of the element OR NOT, characterized in that, in order to increase the reliability and simplify the device, A single pulse shaper and a pulse counter, whose reset input is connected to the majority ele- ment output, are entered. ment, the counting input is with a clock pulse bus, and the output of the last bit is with another input of the OR-NOT element, the output of which is connected to the control input of the single pulse shaper, the clock input connected to the bus clock pulses, the output of the former single pulse generator is connected to the first inputs of the first, second and third elements I, with the output of the device and the input of the element NOT, the output of which is connected to the C-inputs of each trigger, D-inputs of which are connected to the common bus, and R-inputs to the reset bus, inverting the outputs of each trigger connected to the second inputs of the first, second, and third elements, respectively, and the direct outputs to the corresponding inputs of the fourth element, I. / 7 gtll- | aggl .fncfX " I 111 J211 - 3/1 f 7 10119). 11 (20), 12 (21). FIG. 2 Editor A.Gulko Compiled by N. Belinkova Tehred Z.Kastelevich Proofreader E.Sirohman Order 1140/62 Edition 767 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Filial PPP Patent, g, Uzhgorod, st. Design., 4 JlJ-LTLTLrLrirL Tj. g / iggg. / gagf. I -Lr FIG. five