SU461437A1 - Device for asynchronous compaction of communication channels using time division - Google Patents

Description

The aim of the invention is to increase the reliability of a transmission without further increasing the number of bursts in a command by forming such a sequence of commands in which the erroneously received command is automatically corrected by the receiver.

This is achieved by introducing a shift and delay circuit into the device at the transmitting station, a threshold circuit and a trigger, the second output of the elastic memory block being connected via a shear circuit to the corresponding input of the phase detector, the output of which is connected via the threshold circuit to the first input of the shear circuit and to the input of the delay circuit, the output of which is connected to the second input of the shifting circuit and to the first input of the trigger, the second input of which is connected to the output of the command generator, and the output to the unit for changing the read speed, and at the receiving station delay and inhibit schemes, integrating and differentiating circuits and trigger, where the output of the command decoder through the serially connected integrating and differentiating circuits are connected to the first trigger input and to the first input of the inhibit circuit and through the serially connected trigger and delay circuit , the output of which is connected to the input of the recording speed change unit.

The block diagram of the device is shown in the drawing, where: block 1 elastic memory, shear circuit 2, phase detector 3, block 4 changes read speed, delay circuit 5, threshold circuit 6, trigger 7, command driver 8, synchronization transmitter 9, block 10 change recording speed, differentiating circuit 11, integrating circuit 12, trigger 13, decoder of commands 14, elastic memory block 15, phase detector 16, generator 17, low-pass filter 18, delay circuit 19, prohibition circuit 20.

The information is read in by the frequency / n, which comes through the unit 4, the change in the read speed. At the same time, the phase detector 3 receives the write and read pulses from the cells of the elastic memory unit 1 through the shear circuit 2. The output signal of the phase detector 3 is fed to the command generator 8, which, at the corresponding clock positions of the additional channel defined by the synchronization transmitter 9, generates one of the commands depending on the sign of the effective voltage at the output of the phase detector 3. In case 7 of phase detector 0, a command A is formed, corresponding to a decrease in the read speed, if U is a phase detector 0, then a command B is formed, corresponding to an increase in the speed of reading information from the elastic memory block.

However, not each of the generated commands affects the read speed change unit 4, since the pulses corresponding to the generated commands are sent to a trigger, which determines the sequence of action on the read speed change block 4. Due to the presence of the trigger 7 5 after affecting block 4 of command A, only command B can produce the next impact, and vice versa, after influence B of command B, the next impact can be made by command A.

0 When the voltage at the output of the phase detector 3 reaches the threshold level corresponding to the phase shift between / n and / o in one clock interval frequency / w the threshold circuit 6 triggers. The output signal of the threshold circuit 6 acts on the shift circuit 2, causing compensation for this shift at the input of the phase detector 3. A change in the speed of reading information from the elastic memory block does not occur at this moment, since at the receiving station this moment can be detected after transmitting two to four successive commands. For this purpose, a delay circuit 5 is connected to the output of the threshold circuit 6, which can be used as

5 counter or shift register. The signal from the output of the delay circuit 5 acts simultaneously on the trigger 7 and the shift circuit 2. In this case, the phase shift introduced by the circuit 2 after the triggering of the threshold circuit 6 is compensated, and the trigger 7 passes a command of the same sign as the previous one to the block 4.

At the receiving station, the received signal is recorded in the elastic memory block 15 with the frequency fs received from the write speed change unit 10. Information is read from the frequency / s of the signal produced by the generator 17, controlled by the signal from the output of the low-pass filter 18. The input of the lowpass filter 18 comes

0 a signal from the output of the phase detector 16, to the inputs of which the write and read pulses of one of the cells of the elastic memory 15 are received. At the clock positions of the additional channel, the Ifrator of commands 14 receives incoming commands and controls the trigger 13 in accordance with them. not all received commands appear in the output of the trigger, but only part of them. So, after passing to the input of the change speed unit 10 type B command, command A is allowed to pass, and vice versa, after command A command B is allowed to pass. In accordance with the commands passing through trigger 13, the speed change unit makes appropriate changes in the number of recording pulses in a block of elastic memory.

When transmitting phase shifts close to 2n, the sequence of transmitted commands to

0 ustd4stve has the form (- | - +)

or (-I-h ++) depending on

the sign of the current detuning / n and / c. A series of commands of the same name is detected by integrating 12 and

5 differentiating 11 schemes after the arrival of two or four identical teams that replaced the previous series of opposing commands. The signals at the output of the differentiating circuit that appear at these points in time go to trigger 13, which passes the same command to block 10 as the previous one, and the first command that starts a new series of commands of the same name due to the presence of delay circuit 19 and prohibition circuit 20 does not cause a change in the speed of recording information in the elastic memory block.

Since, in the receiving device, not all commands affect the change rate, but only a part of them, incorrect command reception leads to a change in the number of pulses in the restored sequence, but the next correctly received command compensates for this change and the interruption of communication in this case is equal to the period follow commands. During this time, the frame alignment subscriber does not detect a synchronization disorder, and thus the reliability of signal transmission rises without an increase in the number of characters in the command.

Subject invention

A device for asynchronous compaction of communication channels using time division, which contains a block of elastic memory at the transmitting station, the output of which is connected to the first input of the synchronization transmitter through the phase detector, the second input of which is connected to the corresponding input of the command generator and the output which is connected to the corresponding input of the elastic memory block, the output of the synchronization transmitter is connected to the corresponding input of the command shaper, at Conversely, an elastic memory block whose outputs are connected via a series-connected phase detector, a low-pass filter and a generator to the first input of the elastic memory block, the second input of which is connected to the output of the write speed change block, which is designed to increase noise immunity devices entered into it at the transmitting station

shear and delay circuits, a threshold circuit and a trigger, with the second output of the elastic memory block being connected via a shear circuit to the corresponding input of the phase detector, the output of which is connected via a threshold

the circuit to the first input of the shift circuit and to the second input of the delay circuit, the output of which is connected to the second input of the shift circuit and to the first input of the trigger, the second input of which is connected to the output of the driver

commands, and the output is to the read speed change block, and at the receiving station, delay and inhibit circuits, integrating and differentiating circuits and a trigger, and the output of the command interpreter is connected through the serially integrated integrating and differentiating circuits to the first input of the trigger and through the series-connected trigger and the delay circuit is connected to the second input of the inhibit circuit, the output of which is connected to the input of the change speed recording unit.

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