SU588645A1 - System for increasing discrete information validity - Google Patents

Description

one

The invention relates to transmission technology and can be used in systems of unidirectional transmission of discrete information.

A device is known for enhancing the reliability of information dissipation, soda) joining the input combined signal 1 signal "Phase, decoding unit" intermediate storage device, OR element, to one input of which the output signal of the "Phase signal" is connected, and to another input - information sensor output through the encoding unit, the output of the intermediate storage device being connected to one of the inputs of the majority block (Addition, to the other input of which the output of the first memory block is connected, as well as the second memory block 1. However, the known device It does not allow detecting erroneously received discrete information with sufficient accuracy.

The purpose of the invention is to increase the probability of detecting erroneously received discrete information. For this purpose, a counter, shift register, transmission control unit, reception control unit, first, second and third keys, an output memory, additional memory unit 1 and a decoder unit, a comparison unit and a co; , wherein

the outputs of the counter are directly and through the shift register connected to the corresponding inputs of the transmission control unit and the reception control unit, the other inputs of which are connected respectively to the outputs of the Siln Phase receiver and the comparison unit, to the inputs of which the output of the decoding unit is connected directly and through serially connected first key and

additional memory block. The output of the interleave (the weft accumulator is connected to one input of the output accumulator directly, through the switch "Transmit-receive - to another input of the output accumulator, to the additional input of the major addition unit, the output of which is directly and through the additional decoding unit connected to the corresponding output. accumulator, and to the corresponding inputs of the OR element, the counter and the third key, the outputs of which are connected to the inputs of the second memory block connected to the “Transmit-Receive” switch, and through Ora key - to the inputs of the first five llamas block.

In addition, the output of the transmission control unit is connected to the corresponding inputs of the information sensor, the OR element and the switch "Transmit-receive, the output of the reception control unit - to the corresponding

the inputs of the output accumulator, the first and the second 1KL1Och and the switch “Transmission-reception, and the output of the coding block - to the corresponding input of the switch“ Transmission-reception.

The drawing shows a structural electrical circuit of the source device.

The device contains the input signal receiver 1 signal "Phase, decoding unit 2 and intermediate" and the collector 3, element OR 4, to one input of which is connected the output of sensor 5 of the signal "Phase, and to another input - output of sensor 6 of information through the coding unit 7 and the output of the intermediate storage device 3 is connected to one of the inputs of the majority Supplement block 8, to the other input of which the output of the first memory block 9 is connected, as well as the second memory block 10, counter 11, shift register 12, transfer control block 13, block 14 reception controls mom, the first key 15, the second key 16, the third key 17, the output drive 18, an additional block

19, a downstream decoding unit 20, a comparison unit 21 and a switch 22 "Transmit-receive. The outputs of the counter 11 directly and through the shift register 12 are connected to the corresponding 1WDOUTs of the transmission control unit 13 and the reception control unit 14, to the other inputs of which are respectively connected to the outputs of the receiver 1 of the Phase signal and the comparison unit 21, to which the outputs of the decoding unit 2 are directly and through a serially connected first key 15 and an additional memory block 19. The output of the interconnecting accumulator 3 is connected to one input of the output accumulator 18 directly, and through the Switch 22 "Transmit-Receive" to another input of the output accumulator 18, to the auxiliary input of the major addition unit 8, the output of which is directly and through the additional unit

20 decoding is connected to the corresponding input of the output accumulator 18, and to the corresponding inputs of the element OR 4, the counter 11, and the third key 17, the outputs of which are connected to the inputs of the second memory block connected to the Transmit-Receive switch, and through the second key 16 to the inputs memory block 9 memory. In addition, the output of block 13 by transmitting is connected to the corresponding inputs of the sensor b of information, the element OR 4 and the switch 22 "Transmit-receive, OUTPUT of the reception control unit 14 to the corresponding inputs of the output accumulator 18, first key 15, second key 16 and switch 22 "Transmit reception, and the output of the coding unit 7 - to the corresponding input of the switch" Transmit-receive.

The device works as follows.

To start the transfer, the start button and the signal from the output of the block are pressed, 13 the transmission control signal is triggered by the sensor 5 of the signal Phase, which through the OR 4 element outputs the sequence of 3 n elements to the output of the receiving part by pulse and cycle . After transmitting the phasing command of the signal OOM from the output of the transmission block of the transmission for a time equal to the duration / cycles, the information sensor is started and through the switch "Transmit-receive, the counter is started and the third key is opened. At the same time, to the calodym to the binary symbols, outputted from the output of the information sensor, in the coding block is added (nk) verification symbol; / Combinations of (n, k) code are output

devices through the element OR and simultaneously through the switch "Transmit-receive and open third key" are recorded in the second memory block.

After that, KaiK counter 11 counts /

cycles, the signal from the output of the shift register 12 through the transmission control unit 13 again for one cycle starts the sensor 5 of the signal "Phase and closes the third" key 17, then the counter 11 starts the signal from the output of the control unit, the third key 17 and / - element combinations from the output of the second memory block 10 are again output to the device through the element OR 4 and simultaneously recorded in the second memory block. The signal from the output of the transmission control unit 13 in the first transmission / combinations allows them to be output to the output of the device through the OR 4 element from the output of information sensor 6, and during retransmissions from the output of the second memory block 10. At the end of the second cycle of operation of the counter. And for the third time, the sensor of the "Phase" signal is first started, then the counter and the output is again disabled

the device is first supported command, then // r-element combinations from the output of the second memory block 10, while the third key 17 is closed and in third gear combined into the second memory block 10 they are not recorded.

Thus, the output of the device three times a row is given a block of (/ + 1) combinations, the first of which is the phasing command. In the far past, the operation of the device in the “Transfer” mode is the same, except that for the first transfer of the subsequent block from the (/ + 1) combination there is no need to press again the Start / Start button of the transmitting part by the signal from the output of the control block transmission 13.

In the mode "Reception of information from the output of the device element-wisely fed to the inputs of the intermediate storage device 3, decoding unit 2 and receiver 1 of the signal" Fava. AFTER receiving the phasing command by a signal from the output of the receiver of the signal "Phase through the reception control block 14, the switch 22" Transmit-receive starts the counter

11 and the third key 17 is opened, with a signal

with. The output of the reception control unit 14 opens the nepiBbifi key 15. Thus, the recording of information from the output of the intermediate filter 3 to the input of the second memory block 10 and the recording of the signal output from the block 2 decoding "and the input of the additional memory block 19 is allowed. After receiving / combinations, in each row of the second memory block 10, the corresponding l-element combination will be recorded, and in each bit of the additional memory block 19, with an error (“1)” is written or without error (“O) this combination is written was accepted. When the block is re-received from the (/ + 1) combination, counter 11 is restarted, and in the event of a non-receiving phasing command due to distortions caused by interference on the communication channel, the signal for triggering the counter is generated in the reception control block 14 by exit register 12 shift. With noBTOpHOiM reception of the / -comb combinations in block 21 (Comparison, the sign corresponding to the received combination is compared with the sign corresponding to the first time receiving this combination and recorded in a certain bit of the additional memory block 19. After repeated reception of each com: binadium At the output of the comparison unit 21, one of four signals is possible:

00- combination of prgrta and without error both

times;

1: 1 — combination (received with an error both times;

01- combination received without error

the first reception and with an error in the second;

10 - combination received with an error at nepiBiOM reception and without error at the second.

When the first and third signals appear, the keys 17, 16, 15 are closed and the corresponding combination is erased at the output of the intermediate accumulator 3. When the second signal appears, the second key 16 opens with the signal from the output control unit and the received combination is written in 1 first block 9 memory ti. When the fourth signal appears from the output of the receiving control unit, the first and third keys 15, 17 are opened, the received COM is recorded in the corresponding row of the second memory block 10 instead of the Combination recorded there with ne, ditch reception, and in the corresponding bit The memory block 19 erases the indication “I.

At the third reception of a block of (/ - | -1) combinations with a signal from the output of the reception control block 14, counter 11 is restarted in the same way as it was started at the second reception of the block. In this case; in the comparison unit 21, the feature of the received combination is compared with the corresponding feature recorded in the additional storage unit 19. After the third reception of each combination: at the exit

a block of comparison is possible one of four signals:

00 — combination received without error for the third time and without error for the first or second time (or both);

01-combination is received with error for the third time and without error for the first or second time (or both);

10- combination received without error for the third time and with error both the first and

second time;

11- combination received with error all

three times. When the first and (second signal

The output signal from the reception control unit allows recording the corresponding combination to the input of the output accumulator 18 from the output of the second memory block 10, and when the third signal appears, it is the direct output of the intermediate storage device 3. In all three cases, the k-information elements of the combination recorded in the output drive 18, is output to the output of the receiving part.

When the fourth signal appears, the recording to the inputs of the output accumulator 18 and the additional decoding unit 20 from the output of the 8-fold combination block formed by

the element-wise majority addition of the combinations received the first time (from the output of memory block 10), the second time (from output of memory block 9) and the third time (from the output of intermediate storage 3). Upon detection

errors in the newly formed combination, the signal from the output of the additional decoding unit 20, this combination is erased "and the output of the output accumulator 18, in the absence of error, is output to the receiving part.

Thus, the proposed device allows automating the process of error correction in the case of unidirectional information transfer while simultaneously increasing the information transfer rate and the degree of reliability increase.

Formula and 3 optics

A device for enhancing the reliability of discrete information, containing a signal-integrated Phase, a decoding unit and an intermediate storage unit, an OR element, to one input of which the output of the Phase signal sensor is connected, and to another input an output of an information sensor via an encoding unit, moreover, the output of the intermediate storage device is connected to one of the inputs of the majority block

addition, to the other input of which the output of the first memory block is connected, as well as the second memory block, characterized in that, in order to increase the probability of detecting erroneously received discrete information, a counter is entered (register -shift, block