SU563735A1 - Binary signal receiver - Google Patents

Description

The stop distributor is connected to one input of the OR element, to the other input of which the output of the second key block is connected, and the control inputs of the synchronous and start-stop valves, the first and second key blocks and the memory block are connected to the corresponding outputs of the information output control block whose inputs are connected to signal outputs of the control unit, synchronous and start-stop valves.

The drawing shows a structural electrical circuit of a binary signal receiver.

The binary signal receiver contains input drive 1 connected in parallel to the input, the output of which is connected to the input of the element 2, the error detection unit 3 and the decoder 4 service combinations, and the 5th Direction unit, feedback signal generation unit 6, synchronous 7 and startstone 8 distributors , the first 9 and second 10; key block, memory block II, information control block 12 and the OR element 13, with the output of the decoder 4 service combinations and the output of the error detection block 3 through the control block 5, one of which About connected to the second input of the element And 2, connected to the block 6 generating feedback signals, and the output of the element And 2 through a serially connected synchronous distributor 7, the first key block 9, to the inputs of which the inputs of the second key block 10 are connected in parallel, the memory block Both the startstone distributor 8 is connected to one input of the OR element .13, to the other input of which the output of the second key block 10 is connected, the control inputs of the synchronous 7 and start-stop 8 distributors, the first 9 and second 10 key blocks and the block and the memory 11 is connected to the corresponding outputs of the information control unit 12, the inputs of which are connected to the signal outputs of the control unit 5, the synchronous 7, and the start-of-eight distributors.

The binary signal receiver operates as follows.

If all previous combi nation were received correctly (we will call the right method any event that does not have an error detection signal from error detection block 3), then the next correctly received combination from input drive 1 enters the message receiver through an open signal | control unit 5, element AND 2 synchronous valve 7, (Second key block 10 and element OR 13. Synchronous 7 and startstone 8 distributors operate synchronously and in phase). Block 6 forming signals back This link transmits a “Confirmation.

If errors are found in the received combination, it is erased. Formation block 6

C-NaloB back, communication and transmits the reverse channel signal "Request. The control unit issuing information 12 stops start-stop valve 8.

5 The combination received correctly after the combination with the detected error cannot be output to the message receiver, as this would lead to a change in the order of the combinations that occurred when they were received from the message sensor. Therefore, this combination, through the open And corresponding element of the control unit 5, the synchronous valve 7, the first key block 9, opened by the corresponding signal of the information output control unit 12, is written into the AND block, Memory Block II consists of n zones, where the value of n is determined by the time of propagation of the signal in the loop of the transmitter-receiver;

0 transmitter (transmitter repeater capacity). Each zone consists of (m-f-1) memory cells, each of which is designed to record one combination.

Each input combination

5 receivers of binary signals, you can assign the number of a natural row, that is, to number. Then the process of writing combinations into zones of the block of type 11 can be considered as the process of dividing natural numbers into classes of residues modulo n. For example, for 4 and t b it looks like this:

1713951

1814106 2

1915117 3

2016128 4

Combinations recorded in the same} and the same area of the memory block I will be called combinations comparable modulo n. Let us call a combination reception cycle, the conditional numbers of each of which belong to different classes of deductions. A cycle consisting of Combinations that are all erased is called an erasable cycle. At the beginning of the cycle, you can take any combination.

If, after receiving the combination with the detected errors, the next combination is also received with the detected errors, it is erased.

Thus, if the reception cycle begins with the reception of the combination with the detected

in error, each subsequent correctly received cycle combination is written into memory block AND, and each combination with detected errors is erased.

With the beginning of the new cycle, the positions of the synchronous 7 and start-stop 8 distributors coincide. This means that the synchronous valve 7 is connected via the first key block to the input of the t-th zone of the Memory block and is ready to write to it the next received

combination, and start stop distributor

8 is connected to the outputs of the same tth loop and is ready to write off information from it.

If the first combination of this cycle is correct, then the synchronous valve 7 outputs it via the second key block

10, opened by the corresponding signal of the information control unit 12, and the element OR 13 to the message receiver. After this, block 12 starts the start / stop dispenser 8, which provides sequential output via the OR 13 element to the receiver of combination messages from the memory block

11. Moreover, if Start-Stop Valve 8 was connected to the outputs of the t-th zone, then the write-off of combinations begins from the (1- | -1) -th zone with the subsequent transition to the (r- | --2) -th zone and Further. With each access to the memory zone, only one successive combination is deducted. If the next zone, the start-stop valve 8 is connected to the coder, is empty, then it stops regardless of the presence of combinations in the remaining zones. The speed of the start / stop distributor 8 is chosen such that before the end of reception of the second combination of this cycle is written off from the memory block AND all those combinations that can be written off without disturbing their order.

For example, suppose that combinations with conditional sequence numbers 1, 2, 3, 4, 5, 6, 7, 8 are given out at the receiver of messages. Combinations are written in memory unit 11

161310

1411-

that is, 16, 13, 10 combinations are recorded in the first zone, 14 and 11 in the second zone, and the third zone is empty. The new admission cycle begins with the 9th combination admission. Synchronous 7 and start-stop 8 distributors are connected to the 3rd zone. If the 9-combination is received correctly, it is output to the message receiver via the synchronous distributor 7, the second key block 10 and the OR 13 element. Then the information control block 12 starts the start-stop distributor 8, which performs the alternate cheating of the 10th and 11 th combinations. Since the third zone is empty, after connecting the start / stop valve 8 to it, it stops. In the memory block And left

13

16 14

combinations.

If one of the combinations is received once a time with errors detected while simultaneously receiving (t -} -) combinations comparable to the modulus n, then regardless of the results of receiving the other combinations, this state is possible

memory block 11, in which one of its iio.niocrbio zones is filled and further writing to it is impossible. The probability of such an event can be made of an arbitrarily small value by an appropriate choice of the value of m.

The transmitter receives the information about the overflow of the memory block 11 of the receiver by analyzing the state of its similar memory block. In this case, the transmitter transmits an "Rest" service combination, which uses one of the allowed code combinations. With proper reception of the service combination “Rest and with her

received with errors, it is erased in the input drive I.

Thus, the predolled binary signal receiver, using the same order for storing

The combinations that were received from the message sensor, not locking the receiver for the reception time ("+) combinations when an error was detected, but the memory block 11, reduces the amount of re-received information.

Claims (1)

1. V. Vlasov and others. Data transmission equipment. “AK ring, L., VKAC, 1974, p. 32- 54. ; / 1 .Г, /.v,,;jj- - | | | .- FIiiIE i- i -; vi - f f tfloafiaiiaff