SU809620A1 - Device for clock synchronization and regeneration - Google Patents

Description

The invention relates to radio communications and can be used in discrete information transmission systems.

A device for clock synchronization and regeneration, containing serially connected master oscillator and frequency divider, the outputs of which are connected respectively to the inputs of the signal conditioner of the phase zones and to the control inputs of the decoder, to the other inputs of which the outputs of the memory block are connected, as well as the OR element connected in series, the gating block and a shaper of the output signal, while the outputs of the decoder are connected to the inputs of the OR element (1].

However, the known device has low accuracy and noise immunity of synchronization, since the measurement of the size of the mismatch zone is performed on the interval of one package, and the result is determined by the instantaneous signal-to-noise ratio. In addition, in the known device it is impossible to receive short messages and there is a loss of information at the beginning of a communication session and after long interruptions in communication.

The purpose of the invention is to improve the accuracy and noise immunity of synchronization, as well as providing synchronization of short messages and reducing information loss.

This goal is achieved by the fact that the sequentially connected adder, a sum register and a division unit, as well as a signal generator of the analysis zones, a delay element, a register of the number of signal edges and / 15 series signal counter and a threshold 'block the output of which is connected to the combined control inputs of the register of the sum, register of the number of edges, signal and division block and the input of the delay element 20, the output of which is connected to the control input of the memory unit the tee, to the corresponding inputs of which the outputs of the division unit are connected, while the first output of the signal conditioning instrument 25 la analysis is connected to the corresponding input of the bistor® and the first input of the signal edge counter, the second input of which is combined with the control inputs of the phase zone signal generator and adder, and the outputs of the input of the threshold adder, respectively, the outputs form the season.

the structural diagram of the proposed clock synchronization contains the master geneforms, the zone 5 adder 5 counter 6 signal edges,, 8 signal number register, sum register 9, division, delay element 11, memory, decoder 13, DLZ element 15, signal edge counter strobe block 16 through the register, the number of signal edges is connected to the corresponding inputs of the division unit, and the second output of the signal generator of the analysis zones is connected to the control unit, and phase inputs are connected to the inputs

Also introduced a discrete delay line (DLZ), the input of which is combined with the control input of the signal shaper phase eon, and the output. connected to the second input of the gating block

In the drawing, an electrical device.

The device and regeneration of the rarator 1, frequency divider 2, rover 3 of the phase zone signal mator 4, analysis, threshold block 7 fronts block 10 block 12 14 OR, and the driver 17 of the output signal, the output of which is the output of the device, the input of which is the combined inputs of the counter 16 , DLZ 15 and control inputs of the shaper '3' and adder 4.

The device operates as follows.

The signal from the output of the master oscillator 1 is fed to a frequency divider 2, the division coefficient of which is selected in such a way that the frequency of the pulses at the output of its last discharge is equal to the clock. The status code for the bits of the frequency divider 2 is recorded in the signal generator 3 of the phase zones at the moments when the edges of the input signal appear on its control input. The number K of different states of the frequency divider 2 is equal to its division coefficient, the change of states occurs with a frequency equal to the frequency of the master oscillator 1. Thus, the zones are divided into K, the period of the clock width is equal to δ ’each frequency of which

From the first output of the shaper 5 follows a sequence of short pulses corresponding to the beginning of the analysis zones, and from the second - a sequence of short pulses corresponding to the end of the analysis zones. Counter 6 counts the number of signal edges in the analysis zone. Zeroing of the adder 4 and counter 6 at the beginning of the analysis is performed by the pulses arriving at their inputs from the first output of the shaper 5. Each pulse from the second output of the shaper 5 sends a signal to enable the input of the threshold unit 7 to enable the comparison of the number of edges calculated by the counter 6 with the threshold value. In case of increasing the threshold value, the signal from the output of the threshold block 7, which goes to the control inputs of register 8, register 9 of the sum and block, division 10, allows the following operations to be performed one by one: writing a binary code of the number of signal edges in the counter analysis zone 6 in register 8; writing a binary code of a number, which is the sum of the zone numbers in phase with the signal edges of the analyzed analysis zone, from the outputs of the adder 4 to the register 9 of the sum; dividing the number recorded in the register 9 of the amount, by the number represented in register 8, block 10 division.

The signal from the output of the threshold block 7 is received * also on the element 11 delay. After a sufficient time for the operation of division, the output of the delay element 11 to the control input of the memory unit 12 receives a signal enable recording in the memory unit 12 of the binary code number representing the result of the division. The memory unit 12 stores this information until the next signal arrives from the delay element 11. The number recorded in the memory unit 12 is the average during the aeons of analysis, the mismatch of the input signal and clock pulses. The decoder 13 generates a signal at the corresponding output at times when the state of the bits of the frequency divider 2 coincides with the states of the corresponding bits of the memory unit 12. Thus, the clock pulses are shifted by a time equal to the measured average dissonance, recording in the shaper 3 a binary code of eon numbers in phase with the edges of the input signal. Each edge of the signal supplied to the control input of the adder 4, is a signal permit the summation stored in the adder 4 numbers with a zone code in phase with this edge of the signal. Shaper 5 splits the communication session into equal zones.

popping.

The pulses from the output of the decoder 13 are sent to the OR element 14 and then used to regenerate the signal. The input signal is supplied to the DLZ 15, the delay time of which is chosen equal to the sum of the durations of the zone. analysis and delay element 11 delay. In the gating block 16, the clock pulses are shifted by half the burst and the polarity of the input signal is determined at time instants corresponding to the measured positions of the middle bursts. Shaper 17 gives the output of the device a regenerated signal required.

size and standard duration. ^{1 * 3 The} proposed device has increased accuracy and noise immunity of synchronization. In addition, the required phasing accuracy is maintained and synchronism is maintained during communication interruptions and during the transmission of long signals of the same polarity. The device also allows to reduce information loss during synchronization at the beginning of a communication session and after long interruptions in communication and provides reception of short telegrams.

Claims (2)

(54) DEVICE OF CLOCK SYNCHRONIZATION AND REGENERATION of the counter of signal fronts through the register of the number of fronts of the signal are connected to the corresponding inputs of the dividing unit, the second output of the signal conditioner of the analysis zones is connected to the control input of the threshold block and the inputs of the signal phase are respectively connected zones. A discrete delay line (LLL) was also introduced, the input of which is combined with the control input of the phase zone imager, and the output connected to the second input of the gating unit. The drawing shows a structural electrical circuit of the proposed device. The clock synchronization and regeneration device contains a master generator 1, a divider 2 frequencies, a shaper 3 phase zone signals, an adder 4, a shaper 5 signal of analysis zones, a counter of signal fronts, a threshold block 7, a register 8 of the number of signal fronts, a sum register 9, a block 10 divisions, delay element 11 memory block 12, decoder 13, element 14 OR, DLZ 15, gating block 16 and output shaper 17 whose output is the output of the device whose input is the combined inputs of the counter 16, DLZ 1 and controlling form inputs The rotator 3 and the adder 4. The device operates as follows. The signal from the output of the master oscillator 1 is fed to the frequency divider 2, the division factor of which is chosen in such a way that the frequency of the pulses at the output of its last time is equal to the clock frequency. The code of the states of the bits of the frequency divider 2 is recorded in the shaper of the 3 phase zone signals at the instants of appearance at its control input of the fronts (drops) of the input signal. The number K of different states of the divider of part 2 is equal to its division factor; the change of state occurs at a frequency equal to the frequency of the master generator 1. Thus, the clock frequency period is divided into K zones, the width of each of which is equal and the writing is made in the driver 3 binary code of zone numbers, common-mode fronts of the input signal. -Each signal front, arriving at the control input of the adder 4, represents the summing signal stored in the adder 4 numbers with an area code in-phase with the given edge of the signal. Shaper 5 breaks the communication session into equal zones. From the first output of the imaging unit 5, a sequence of short pulses corresponding to the beginning of the analysis zones follows, and from the second output - a sequence of short pulses corresponding to the end of the analysis zones. Counter B calculates the number of signal fronts in the analysis zone. The zeroing of the adder 4 and the counter 6 at the beginning of the analysis zones is carried out at their inputs by pulses from the first output of the former 5. Each pulse from the second output of the former 5 to the control input of the threshold unit 7 is given a resolution comparing the number of fronts counted by counter b with a threshold value. In the case of an increase in the threshold value, the signal from the output of threshold block 7, arriving at the control inputs of register 8, sum register 9 and block, division 10, permits the following operations to be performed in turn: write the binary code of the number of signal fronts in the analysis zone of counter 6 in register 8; writing the binary code of the number, which is the sum of the numbers of the zones in-phase to the fronts of the driven zone of the analyzed zone, from the outputs of the adder 4 to the register 9 of the sum; dividing the number recorded in the register of 9 sums by the number represented in register 6 by block 10 dividing. The signal from the output of the threshold unit 7 also goes to the element 11 of the delay. After a time sufficient for the division operation to expire, the output of the delay element 11 to the control input of the memory unit 12 receives a write enable signal to the memory unit 12 of the binary code of the number representing the result of the division. The memory unit 12 stores this information until the next signal arrives from delay element 11. The number recorded in memory unit 12 is the average mismatch of the input signal and clock pulses during the analysis zone. The decoder 13 outputs a signal at the corresponding output at times when the bits of the splitter 2 frequency coincide with the states of the corresponding bits of the memory 12. In this way, the clock pulses are shifted by a time equal to the measured average error. The pulses from the output of the decoder 13 arrive at the OR element 14 and then are used to regenerate the signal. The input signal arrives at the DLL 15, the delay time of which is chosen equal to the sum of the durations of the analysis zone and the delay of the delay element 11. In gating block 16, a clock is shifted by half of the parcel and the input signal is determined by the polarity of the input signal at times of time corresponding to the measured positions of the middle of the parcels. The shaper 17 provides a regenerated signal of the required size and standard duration to the device output. The proposed device has a high accuracy and noise immunity synchronization. In addition, the required phasing accuracy and preservation of synchronism in communication interruptions and in the transmission of long-term signals of one polarity are ensured. The device also reduces information loss during synchronization at the beginning of a communication session and after long interruptions in communication and ensures reception of short telegrams . Claims 1. The clock synchronization device 1.1III and regeneration, containing sequentially connected master oscillator and frequency divider, the outputs of which are connected respectively to the inputs of the phase zone signal conditioner and to the control inputs of the decoder, to the other inputs of which are connected the outputs of the memory block, As well, therefore, the connected OR element, the gating unit and the output driver are connected, the outputs of the decoder are connected to the inputs of the OR element, characterized in that, in order to increase The accuracy and noise immunity of synchronization, a series-connected adder, a per-sum sum and a dividing unit, as well as a signal generator of analysis zones, a charge element, a number of signal edge register and a series connected signal edge counter and a threshold block whose output is connected to the combined controlling the input register of the sum register, the register of the number 1 ynto8 of the signal and the dividing unit and the input of the delay element whose output is connected to the control input of the block, to the corresponding inputs of which The outputs of the divider are connected, the first output of the signal generator of the analysis zones is connected to the corresponding input of the adder and the first input of the counter of the signal fronts, the second input of which is combined with the control inputs of the signalizer of the phase zones and the adder via the number register the signal fronts are connected to the corresponding inputs of the dividing unit, the second output of the forcing signal of the analysis zones is connected to the control unit for the input of the threshold unit, and to the inputs of the adder but the outputs of the phase shaper signal are connected. 2. The device according to claim 1, so that, in order to ensure the synchronization of short messages and reduce information loss, a discrete delay line has been introduced, the input of which is combined with the control of the input of the phase signal generator zones, and the output is connected to the second input of the gating unit. Sources of information taken into account during the examination 1. USSR Author's Certificate No. 594594, cl. H 04 L 7/02, 1976 (protype).