SU1469556A1 - Frequency jitter meter - Google Patents

Abstract

The invention relates to communication technology and can be. used to control the quality of communication channels. The purpose of the invention is to improve the accuracy of measuring phase jitter in both digital and analog communication systems. This is achieved by introducing into the device the pulse generator 5, the phase detector 21, the low frequency filter 24, the rms 25 pulses, and the selection unit 29: the clock frequency support .1, which contains the phase advance delay and late delay unit 7, the block 11 determine the mean phase value, RS triggers 13, 18, elements AND 14, 15, decoder 20, counter 22, comparison unit 23 and counting trigger 26. The device generates two regular pulse sequences from a pseudo-random linear signal. In this case, one of the sequences is formed as a reference highly stable pulse signal, and the second repeats the phase fluctuations of the linear signal. Both of these sequences are fed to a phase detector 21, where the envelope of the measured phase jitter, which is then fed to the indicator, is highlighted. 2 hp f-ly, 5 ill. (L

Description

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The invention is from service to communication technology and may be used to monitor the quality of communication channels.

The purpose of the invention is to improve the accuracy of measuring jitter in both digital and analog systems,

FIG. 1 shows a structural electrical circuit of the device for measuring the phase jitter 5 in FIG. 2, and time diagrams of the operation of the device are given; in fig. 3 shows the scheme for the implementation of one block of the definition of on-hold and phase delay; Fig. 4 is the same; another determination unit is ahead of the phase delay; in fig. 5 is a diagram for constructing a block for determining the average phase value.

The device consists of a matching unit 1, a rectifier 2, a quadratic detector 3, an indicator 4, a driver 5 pulses, a block 6, 7 for determining the phase advance and delay, the accumulator 8, the element:

IfflH 9, KZ-flip-flop 10, block 11 for determining the average phase value, decoder 12, E-Ya flip-flop 13, first element 14, second element 15, block 16 comparison, counter 17, RS flip-flop 18, counting trigger 19s a decoder 20, a phase detector 21, a counter 22, a comparison unit 23, a low frequency filter 24, a pulse generator 25, a counting trigger 26, a block, 27 averaging. Clocks 6, 8s 9, 10, 12, 16, 17, 19 o6pa3; snoT node

28 clock selection; blocks 7,11, 13, 14, 15, 18, 20, 22, 23, 26 - reference clock selection node 29.

Block 6 (Fig. 3) for determining the phase advance and lag consists of AND 30 - 35 elements, formers 36-39 1 & shulsov, RS-44 triggers, elements ШИИИ 45, 46, delay elements 47, 48, counters 49, 50, node 51 key elements, and node 52 elements OR.

Block 7 (Fig. 4) for determining the phase advance and delay consists of: switches 53 54, elements OR 55, 56, elements AND 57 - 64, formers 65-70 pulses, RS-triggers 71 - 76, delay elements 77, 78, counters 79, 80, decoders 81, 82, counting trigger0

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83, node 84 elements OR, node 85 key elements.

Block 11 (Fig. 5) of determining the media 1, its phase value consists of drivers 86 - 88 pulses, 89 delays, elements AND 90 - 92, elements OR 93 - 95, inverter 96, RS flip-flops 97, 98, first counter 99, element 100 comparisons, a decoder 101 and a second counter 102.

A device for measuring phase jitter works as follows.

A digital or analog signal is fed to the input of the device on the communication line or from the output of the regenerator (in the case when the phase jitter of the pulse sequence is measured).

Consider the operation of this device for the most difficult case, when a pseudo-random digital signal arrives at its input (Fig. 2a), the duty cycle between pulses in which varies randomly.

The operation of the proposed device is based on the formation of a pseudo-random linear signal of two regular pulse sequences corresponding to the voltage of the clock frequency of the given communication system. In this case, one of the sequences is formed as a reference highly stable impulse signal. The second pulse sequence is formed so that it repeats the phase fluctuations occurring in the digital linear signal at the input of the device. Both regular pulse sequences are fed to a phase detector where the envelope of the measured jitter is detected. The fluctuating analog voltage after passing through the filter. a low frequency square detector and averaging unit is applied to the indicator.

Before starting, all the triggers and counters included in this device are set to their original state.

The signal from the input of the device (Fig. 2a) falls to the input of the matching unit 1. The matching unit I provides the necessary input impedance of the device for interfacing with the measured communication channel. In addition, in this block the effort is made

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signal signaling (possible using AGC), and in the case where the signal is a unipolar binary sequence (e.g., as in the LM-1 2 system), the signal is differentiated. From the output of block 1, the signal is fed to the input of the top of the sensor 2, where its full-wave rectification is carried out (without filtering). The smaller signal (FIG. 26) is fed to the input of the former 5. In this block, short pulses are formed along the leading edges of the higher signal (Fig. 2c). Short pulses from the output of the former 5. are fed to the first inputs of the blocks. 6, 7 determine the advance and the late phase. At the second inputs of the blocks 6, 7, high-frequency pulses (Fig. 2d) are received from the pulse generator 25. The third and fourth inputs of block 6 are supplied with rectangular pulses (the frequency of which corresponds to the clock frequency of the monitored communication system) from the inverse. and direct outputs of the first counting trigger 19 (Fig. 2e, e).

The third and fourth inputs of block 7 also supply rectangular pulses from the inverse and forward outputs of the counting trigger 26 (Fig. 2m, n

The pulse sequence from the output of counting trigger 26 is a highly stable reference signal, with which the pulse sequence is compared, obtained at the output of counting trigger 19 and repeating phase fluctuations have a place in the signal at the input of the device.

The formation of a phase fluctuating regular pulse sequence. (Fig. 2d, e) is as follows.

In block 6, the phase (moment of appearance) of each pulse from the output of the imaging unit 5 (Fig. 2c) is compared with the phase (transition moment from 1 to O and from O to 1) of rectangular pulses from the outputs of the counting trigger 19 (Fig. 2e, e). The time interval corresponding to the phase difference of these compared pulses is filled with high-frequency pulses from generator 25 (Fig. 2d). Moreover, the greater the phase difference between the compared ones

 pulses, the greater the number of you

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low-frequency pulses from the generator. Pa 25 decreases in the time interval corresponding to the one given difference of phases. The high-frequency filling pulses are counted by a counter in block 6, and at its code output code combinations appear, corresponding in binary expression to the magnitude of the phase difference between the signals being compared,

In block 6, there are also first and second control outputs. Short pulses that appear at the first control output of block 6 (Fig. 2g) correspond to such a state when the phase of the pulses from the output of the former 5 (Fig. 2c) is ahead of the phase of the pulses from the output of the counting trigger 19 (Fig. 2e) . The occurrence of the same short pulses at the second control output of block 6 (Fig. 2h) corresponds to the position when the phase of 1-1 pulses from the output of the driver 5 is delayed relative to the phase of the pulses from the output of the counting trigger 19.

Code combinations from the code output of block 6, corresponding to the phase difference between the compared signals, are fed to the code input

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pit 8, but not written into it. A code combination is recorded in the accumulator 8 only when a short pulse arrives from its first or second control output at its control input. block 6 through the element OR 9 (fig.2zh, g).

The code combination, recorded in drive 1, 8, appears at its output and is fed to the code input of the decoder 12. The decoder 12 converts the code combinations from the output of block 6, corresponding to the differences between the signals from the outputs of the driver 5 and the counting trigger 19, into code combinations corresponding to the duration of unit clock intervals for a given communication system.

Consider for example the case when the duration of a single clock interval can be represented by 1024 high-frequency pulses from the output of the generator 25. This number of pulses (1024), corresponding to the duration of the undistorted clock interval, is represented by the binary number 10000000000.

1A69556

: Such a binary number is set at the code output of counter 7 after filing — on its information flow 102A, a pulse generator from the output of generator 25. Binary number 10000000000 (from the output of counter 17 is fed to the input code input of the comparison unit 16. For matching the comparison unit 16 it is necessary that its first code input contains exactly the same binary number, therefore, in the absence of a phase signal between the linear signal pulses (driver output 5) and clock pulses (input of the first counting trigger 19) at the output of the decoder 12 O are only .IDA code combinations of 10000000000 (1024), which, in turn, are clocked (Fig. 2d, e), where the moments of the transition from O to 1 and from 1 to O correspond exactly to the same moments in the undistorted linear signal (Fig. 2a) at the input of the device.

At close, but not equal to the value of the phase of the pulse of a linear signal (input block 6) with the phase clock. a pulse (3 and inputs of block 6) at code output of block 6, for example, code combination 0000000001 appears. This code combination is fed to the code input of accumulator 8. In addition, a short pulse (Fig. 2g) appears on one of the two control outputs of block 6 (for example, the first), indicating that the phase of the information pulse (the output of the generator 5) is ahead of the phase of the clock 1c-1pulse (counting trigger 19), which is fed from the first control output of block 6 to the first input of the element OR 9 and through it to the control input of the accumulator 8. Under the action of this pulse, the drive 8 records the code combination 0000000001, and it appears at its output. This combination is fed to the code input of the decoder 12. I Pulse from the first control

The output of block 6 is fed to the R-input of the RS-flip-flop 10, the inverse output of which will be the voltage of a logical unit (Fig. 2ic), and on the direct output the voltage of the logical zero, (Fig. 2i). Signals from the direct and inverse outputs of the RS flip-flops 10 are fed to the first and second additional signals.

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technical inputs of the decoder 12 and up. higher bits are added to the code combination present at the code input of the decoder 12. Then the code combination 100000000001 will be at the input of deganfrarator 12; decoder 12 performs the conversion of this code code; combinations c. the combination 0111 11 11100 (1023). the code combination is fed to the first input of the comparator unit 16, the second code input of which receives continuously varying code combinations from the code output of counter 17. When the information input of the counter 1023 arrives from the generator 25, the code output of the counter 17 appears code combination 0111 1111 11 1 (1023).

At a certain point in time, the same code combinations appear on the first and second code inputs of the comparison block 16, as a result of which a short pulse appears at its output (Fig. 2L). Under the action of this pulse, the counter 17 is reset to the zero state, and also the counting trigger 19 is triggered. A logical unit voltage is applied to the forward output of the counting trigger 19. The consequence of all this will be shortening the duration of the formed clock interval of the signal at the output of the counting trigger 19 (Fig. 2d, e, l) by the amount of one period of high-frequency filling pulses from the oscillator 25. As a result, the phase of the clock pulses turns out to be exactly adjusted to the phase of the input information pulses

During pauses in the arrival of information pulses on the nerves of the input of block 6 (with a pseudo-random digital information signal in lithium) the code output of this block will be code combination i 0000000000. This code combination with the arrival of a short pulse from the first or second control output 50 of block 6 write to drive 8. In decoder 12 to this code combination, logical zero voltages are added to its higher bits: and units from the direct and inverse outputs of the RS flip-flop 10. As a result, h code va combination 10000000000 or codeword 010000000000. Both

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code combinations a decoder .12- converts into a code combination 10000000000 (1024) corresponding to the undistorted clock interval of the signal at the output of the counting trigger 19.

Consider the case when the phase of the input information pulse (the output of the driver 5) is slightly behind the phase of the clock pulse (the output of the counting trigger 19).

Let the code output of block 6, as in the previously considered case, be the code combination 00000000001 This code combination is fed to the code input of accumulator 8. In addition, a short pulse appears on the second control output of block 6, indicating that the input pulse is late clock Under the action of this pulse, the code combination attached to the code input of the accumulator 8 is recorded into it and appears on its code output (code decoder 12). At the same time, under the action of the same pulse applied to the S input of the RS flip-flop 10, it overturns and the voltage of a logical unit appears at its forward output, and the voltage of a logical zero appears at the inverse. These voltages are applied to the first and second additional inputs of the decoder 12. As a result, the code combination 0100000000001 is formed at the input of the decoder 12. The decoder 12 converts this combination into the code combination 100000000001 (1025), which is applied to the first code input of the comparison unit 16. A continuously varying code combinations from the output of counter 17 are supplied to the second code input of the comparison unit 16. When the code combinations match, the first and the second code inputs of the comparison unit 16 will produce a short pulse at its code output (Fig. 2L). With this pulse, firstly, the counter 17 is reset, and secondly, under its influence the counting trigger 19 is triggered. As a result, the duration of the clock interval of the signal at the output of the counting trigger 19 is increased by one period of high-frequency filling pulses (from generator 25 ), which corresponds to the phase adjustment of the clock pulse

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ca under the phase of the input information pulse.

The largest value of the phase difference between the information pulse and the phase of the clock pulse for this device can be chosen equal to half the clock interval. This corresponds to 512 filling pulses from generator 25 and a combination of 10000000000 at the code output of block 6. When the information pulse at the device input advances a clock pulse phase by half a clock interval (512 filling pulses) at the code input of the decoder 12 (together with two additional inputs), a code combination 101000000000. This combination is converted in de-generator 1 2 to code combination 01 000000000 (512).

When the phase of the information pulse lags behind the clock pulse phase by half the clock interval (512 fill pulses), the code combination 011000000000 (1536) is formed at the decoder 12 code input (together with two additional inputs).

Next, a code combination (e.g., 11000000000) is applied to the first code input of the comparison unit 16, to the second code input of which the combinations from the output of counter -17 are continuously received. After 1536 pulses applied to the information input of counter 17 from generator 25, the code combination 110000000000 appears at the output of this counter, which is fed to the second code input of the comparison unit 16.

Since the code combinations at both inputs of the comparison unit 16 are the same, a short pulse appears at its output. With this pulse, the counter 17 is reset to its original state, and, in addition, under the influence of this pulse, the counting trigger 19 is triggered. The output of the counting trigger 19 turns out to have a generated pulse whose duration has become 1.5 clock intervals or 1536 fill pulses. As a result, the phase of the clock pulses at the output of the account 914

Trigger 19 turned out to be exactly tailored to the phase of the information signal at the device input.

Thus, any change in the phase of the input pulses relative to the clock pulses (output of the counting flip-flop 19) is always completed by adjusting the phase of the data of the clock pulses to the phase of the input signal. As a result of the operations performed, a transition occurs from a linear signal with a random duty cycle (Fig. 2a) to a regular pulse sequence (Fig. 2e), while preserving the information about the phase jitter of the signal. This was to be done in order to eliminate the effect of the random linearity of the linear signal on the measured jitter. Without this conversion, measuring phase fluctuations in a digital signal with a random duty cycle between pulses would not be possible.

The regular clock oscillation (Fig. 2d) from the output of the counting trigger 19 goes to the first input of the phase detector 21. However, to isolate the envelope of the phase fluctuations from this signal, it is necessary to have a highly stable reference oscillation. This oscillation is obtained with the help of blocks 7, 11, 13, 14, 15, 18, 20, 22, 23, 26, which form the reference clock selection node 29.

The formation of a highly stable pulse sequence

.

(Fig. 2m, n) is carried out as follows.

In block 7, the phase (moment of appearance) of the pulse from the output of the former 5 (Fig. 2c) is compared with the phase of the rectangular pulses coming from the direct and inverse outputs of the counting trigger 26. The presence of an advance or a delay of the phase of information pulses appears in the appearance at the first or second control input of the block 7 short pulses (Fig 2o, p). These signals are fed to the R- and S-inputs of the RS-flip-flop 13 and to the second and third inputs of the block 11 for determining the average phase value.

When the first control output (Fig. 2o) appears in block 7, a short pulse (indicating

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The phase advance of the information pulse with respect to the clock pulse) RS-trigger 13 is set to such a state that its inverse output is the voltage of a logical unit, and the forward voltage is the logic zero voltage (Fig. 2p, s). These voltages are applied to the first inputs of the first and second elements 14, 15, however, they do not pass through them, since the second inputs of these elements are supplied with a logic zero voltage from the output of block 11 for determining the average phase value.

The first input of block 11 receives high-frequency pulses (Fig. 2d) from the output of generator 25, the fourth input of block P supplies voltages of logical zeros and ones from the direct output of RS flip-flop 13, and the fifth input of block 11 receives short pulses ( Fig. 2x) from the output of comparison unit 23. The moments of occurrence of pulses at the output of block 11 in the stationary mode of operation of the measuring device correspond to the average values of the phase of the information signal at the input of this device. A short pulse from the output of block 11 (fig. 2t) goes to the second inputs of the first and second elements 14, 15, but passes only through the first element 14, since the potential of the logical unit from the inverse acts on its first input the output of the RS flip-flop 13. This short pulse is applied to the K-input of the RS flip-flop 18 and tilts it. At the inverse output of the RS flip-flop 18, the potential of a logical unit appears, and at the direct output, the potential of a logical zero. The code combination 10 is applied to the first and second inputs of the decoder 20. The decoder 20 converts this code combination to code combination 0111111111111 (1023) on the basis of which high-stable clock pulses shortened by one period are formed (Fig. 2m), This is originated as follows in a way. The code combination 011111111П (lb23) is applied to the first code input of the comparator unit 23. The second code input of block 23 from the code output of the counter 22 receives continuously varying code combinations proportional to the number

n

high-frequency pulses arriving at the information input of the counter 22.

At the moment of the coincidence of code combinations 0111111111, a short pulse appears at the first and second code inputs of the comparator unit 23 (Fig. 2x). This impulse firstly resets the counter 22 to the initial state, and secondly, causes the counting trigger 26. The code combination 01111111111 (1020 continues to be present at the first code input of the comparison unit 23 for a long time), then the counting output the trigger 26 is formed by clock pulses, the duration of a unit interval in which is 1023 high-frequency pulses from the generator 25.

When short pulses (Fig. 2p) appear on the second control output of the block 7, indicating a phase lag from the information pulses relative to the clock, the RS-flip-flop 13 is set to the state where its inverse output will be the potential of a logical zero, and on the real — the potential of a logical unit. These voltages are applied to the first inputs of the first and second elements AND 14, 15 (Fig. 2p, c).

A short pulse that occurred at the output of block 11 (Fig. 2T) passes through the second element 15 and causes the RS flip-flop to trigger 18. At the inverse output of the RS flip-flop 18, a logical zero potential appears, and at the direct potential logical unit (Fig. 2y, f). The code combination 01 from the outputs of the RS flip-flop 18 is applied to the first and second inputs of the decoder 20. The decoder 20 converts this code combination to the code combination 10000000001 (1025), on the basis of which highly stable clock pulses increased by one period of filling pulses (Fig. 2m) are generated. ).

The result of the work of the described blocks will be the presence of a highly stable reference oscillation at the output of the counting trigger 26. In this case, the phase of this signal corresponds to material469556

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expectation signal.

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Clock pulses, fluctuating in phase (from the output of the counting trigger 19), and highly stable reference clock :; (from the output of the counting trigger 26) are respectively supplied to the first and second inputs of the phase detector 21. From the signal from the output of the phase detector 21, the low-frequency jitter voltage is extracted from the output signal of the low-frequency filter 24

5 is a noise-like oscillation (Fig. 2c). This voltage is then applied to the input of the quadratic detector 3. The signal from the output of the quadratic detector 3 is fed to the input of averaging unit 27, which represents, in the simplest case, the integrating circuit. After averaging, the voltage is proportional to the root-mean-square value of phase

5 zhani, is fed to the input of indicator 4.

Claims (3)

1. An apparatus for measuring phase-jitter, comprising a series-connected matching unit and a rectifier, a clock selection unit, a quadratic detector, an averaging unit and an indicator, characterized in that, in order to improve the accuracy of measuring phase jitter, as in digital, and in analog communication systems, a pulse generator and serially connected pulse generator, a reference clock selection node, a phase detector and a low frequency filter, the output of which is connected to the input kva, are introduced of the valid detector, the output of the rectifier is connected to the input of the pulse generator, the output of which is connected to the first input of the clock selection unit, the output of which is connected to another input of the phase detector, the output of the quadratic detector is connected to the input of the averaging unit, the output of which is connected to the input of the indicator, and the output the pulse generator is connected to the second and third inputs of the clock extracting node and to the second, third, and fourth inputs of the reference clock selection node. five 0 five 0 1314 2. The device according to claim 1, about the type of TeMj that the clock extracting node contains a series-connected block defined. phase advance and delay, a drive, a decoder, a comparison unit and a counting trigger, an OR element, included in the chalk at the first and second control outputs of the phase advance and latency determination unit and a drive control input, an RS trigger, whose inputs are connected to the element inputs OR the outputs are connected to other inputs of the decoder, a counter whose outputs are connected to other inputs of the comparison unit, the output of which is connected to the control input of the counter, while the second input of the advanced determining unit is In this case, the eases and the counter input of the counter are the second and third inputs of the clock selection node, respectively, the output of which is the first output of the counting trigger connected to the third input of the phase detection and delay unit, the fourth input of which is connected to the second output of the counting trigger. 3. The device according to claim 1, characterized in that the node allocating the reference clock frequency comprises a series-connected unit for determining the advance and delay of the phase, the RS nerve trigger, the first AND element whose input is connected Phi. 2 ten 9556 15 The dinene output is an average phase value determination unit, a second RS trigger, another input connected to the output of the second element AND, a decoder, a comparison unit whose other inputs are connected to the counter outputs, and a counting trigger whose first output is the output of the selection node the reference clock frequency, wherein the first and second inputs of the phase advance and lag unit are respectively the first and second inputs of the reference clock selection node, and the third and quarter inputs are connected respectively With the second and first outputs of the counting trigger, the first input of the average value determining unit. The phase and the counting input of the counter are the third and fourth inputs of the reference clock selection node, respectively; the second and third inputs of the average phase value are connected to the first and the second outputs of the phase detection and latency block connected to, another input of the first RS flip-flop, the second output of which is connected to the fourth input of the average phase value determination block, the fifth input otorrhea connected to the unit and comparing vy.hodom unravl yuschim input counter nerve enters the second member 35 and connected to a second output of the first RS-flip-flop and a second input coupled to an input of the first element vtorm I. 20 25 thirty ig. ftsg.5.