RU2080608C1 - Meter of spectral characteristics of radio signals - Google Patents

Abstract

FIELD: instruments for radio engineering. SUBSTANCE: device has dispersion spectrum analyzer and amplitude detector, first and second pulse generators, first and second comparison circuits, synchronization unit, AND gate, analog-to-digital converter, memory unit and register, recording unit, first, second and third counters, multiplexer, second register, second AND gate, delay gate, OR gate and logical one potential source. EFFECT: increased functional capabilities, in particular, possibility to calculate average frequency and spectral width of radio signals. 3 dwg

Description

 The invention relates to radio engineering measurement and is intended to calculate the average frequency and spectral width of the radio signals.

 Devices are known in which information about the measured spectrum of radio signals is output in digital form (see article Gautier H. Iournois P. Signal processing using surface acoustic ware and digital components. IEE Proc. Pt. F, 1980, v. 127, No. 2, p 92-98, Fig. 5). Such a device contains a series-connected time compressor, a dispersive spectrum analyzer and an analog-to-digital converter (ADC), as well as a synchronizer, the corresponding outputs of which are connected to the control inputs of a temporary compressor, a dispersion analyzer, and an ADC. The device operates as follows. Information about the input signal is recorded in the memory of a temporary compressor, which is implemented on the basis of a digital element base and is a series-connected 2nd ADC, a digital memory unit, and a digital-to-analog converter. The signal from the output of the temporary compressor is fed to a dispersion analyzer, the envelope of the output signal of which corresponds to the amplitude spectrum of the input signal. Using the ADC, the spectrum information is converted to digital form and transmitted further to a digital computer, where parameters such as the average frequency and spectrum width should be calculated. The accuracy of such a device is limited due to the limited dynamic range of high-speed output ADCs (the number of binary bits does not exceed 6-8). In addition, the limited speed of a digital computer can lead to difficulties in calculating parameters in real time.

 Of the known closest in technical essence to the claimed object is a meter of spectral parameters of signals (ed. St. USSR N 1825148, 1993). The device contains a series-connected dispersive spectrum analyzer, a delay line, an amplitude detector and a comparison node, as well as a peak detector and a divider connected in series, the output of which is connected to the second input of the comparison node. The input of the peak detector is connected to the output of the analyzer, the input of which is the input of the device. The device also contains a time slot meter and a synchronizer, the corresponding clock outputs of which are connected to the clock inputs of the dispersion analyzer and a time slot meter. The device also includes a second amplitude detector, a second comparison node, a duration selector and a pulse shaper, the output of which is connected to the zeroing input of the peak detector, as well as a second shaper and the element And, the output of which is connected to the input of the time interval meter, in series. The device also contains a shift register, the input of which is connected to the output of the first comparison node, and the output to the second input of the element And, the second inputs of the comparison nodes are combined, the input of the second amplitude detector is connected to the output of the dispersion analyzer, and the clock input of the shift register is connected to the clock input of the meter time intervals and clock output synchronizer.

 This device operates as follows.

с выхода амплитудного детектора, то есть определяется максимально возможной шириной спектра сигналов, обрабатываемых устройством. По фронту импульса с выхода селектора запускается первый формирователь, который вырабатывает импульс длительностью t_ф1. Величина t_ф1 тоже определяется максимально возможной шириной спектра обрабатываемых сигналов. Импульс с выхода первого формирователя поступает на обнуляющий вход пикового детектора. В первом узле сравнения производится сравнение задержанного на время t_л3 сигнала с выхода первого амплитудного детектора с уменьшенным в два раза сигналом с выхода пикового детектора. Величина t_л3 выбирается таким образом, что она должна быть максимальной длительности отклика с выхода амплитудного детектора, то есть тоже определяется возможной шириной спектра обрабатываемых радиосигналов. На выходе первого узла сравнения формируются прямоугольные импульсы, которые задерживаются в цифровом сдвиговом регистре на время t_р. Величина t_р выбирается таким образом, чтобы во всех возможных ситуациях импульсы на выходе резистора вписывались по времени в импульсы фиксированной длительности t_ф2, формируемые вторым формирователем. Величина t_ф2 определяется тоже максимально возможной длительностью полезного отклика. В результате этого на выход элемента И проходят только импульсы, характеризующие главные лепестки импульсных откликов вида

с выхода первого амплитудного детектора. В измерителе временных интервалов производится подсчет задержки импульсов с выхода элемента И. Поскольку задержка центра тяжести импульсов пропорциональна средней частоте, а длительность ширине спектра, то в измерителе происходит регистрация этих спектральных параметров.A radio signal is input to the dispersion analyzer. As a result, a radio-frequency oscillation is formed at its output, the envelope of which corresponds to the spectrum of signals at the input of the device. At the output of the second amplitude detector, the envelope of this oscillation is extracted, which enters the first input of the second comparison node, the second input of which receives a signal that is twice reduced in amplitude by a peak from the peak detector. At the output of this comparison node, rectangular pulses are formed, the high level of which corresponds to an excess of the signal level at its second input over the signal level at its first input. These pulses are fed to the input of the selector. Only those pulses whose duration exceeds the value of t _s pass to the selector output. The value of t _c is selected based on a priori specified maximum duration of responses of the form

from the output of the amplitude detector, that is, it is determined by the maximum possible width of the spectrum of signals processed by the device. On the front of the pulse from the output of the selector, the first driver is launched, which generates a pulse of duration t _f1 . The value of t _{f1 is} also determined by the maximum possible width of the spectrum of the processed signals. The pulse from the output of the first shaper enters the zeroing input of the peak detector. In the first comparison node, the signal delayed by the time t _l3 from the output of the first amplitude detector is compared with the signal from the output of the peak detector halved. The value of t _l3 is chosen in such a way that it should be the maximum duration of the response from the output of the amplitude detector, that is, it is also determined by the possible width of the spectrum of the processed radio signals. At the output of the first comparison node, rectangular pulses are formed, which are delayed in the digital shift register for a time t _p . The value of t _p is chosen so that in all possible situations, the pulses at the output of the resistor fit in time into pulses of a fixed duration t _f2 formed by the second shaper. The value of t _f2 is also determined by the maximum possible duration of the useful response. As a result of this, only impulses characterizing the main lobes of impulse responses of the form pass to the output of the element And

from the output of the first amplitude detector. In the time interval meter, the pulse delay is calculated from the output of element I. Since the delay of the center of gravity of the pulses is proportional to the average frequency and the duration of the spectrum width, these spectral parameters are recorded in the meter.

 The disadvantage of this device is the ability to skip signals in the case of a large range of the likely width of their spectrum. The parameters of such nodes that make up the device, such as pulse shapers and a delay line, are determined by the maximum width of the spectrum. If, for example, this indicator is equal to the bandwidth of the dispersion analyzer, then the temporal parameters of the formers and the delay line are the maximum possible. As a result, narrower signals of lower intensity, the frequency interval between which is less than the a priori specified maximum spectral width, will be skipped.

 The essence of the proposed technical solution lies in the fact that the device containing the dispersion spectrum analyzer and an amplitude detector in series, the analyzer input being the device input, the first and second comparison nodes, the first inputs of which are combined, the first and second pulse shapers, the converters of which are combined, a synchronizer, the first output of which is connected to the synchro input of the dispersion analyzer, and element And, an analog-to-digital converter, an opera unit, are connected in series an internal memory and a register, the information input of an analog-to-digital converter connected to the second output of the synchronizer, and the output to the first inputs of the comparison nodes, the register input connected to the second input of the first comparison node, and the output to the second input of the second comparison node, the output of which is connected to the input element And, the recording unit, the second register, the output of which is connected to the information input of the recording unit, the second information input of which is connected to the second output of the first register, and the clock input is output the house of the And element, the first counter whose output is connected to the second input of the RAM node and to the input of the second register, the second and third counters, a multiplexer whose inputs are connected to the outputs of the second and third counters, and the output with the address input of the memory node, the recording input of which connected to the output of the first driver, the input of which is connected to the counting input of the first and counting input of the second counters, as well as to the address input of the multiplexer, and the second input of the synchronizer, the second element And, the first stroke of which is connected to the output of the first comparison node, and the second input is combined with the second input of the first AND element and the output of the second driver, the delay element and the OR element, the output of which is connected to the installation input of the first register, the first input to the installation input of the first counter and to the third output of the synchronizer, and the second input to the output of the delay element, the input of which is connected to the sync input of the second register and the output of the first element And, the second input of the first register is connected to the second output of the RAM node, and the third input to the source logic-one building, the clock to the count input of the third counter and the output of the second AND gate and the third output to the adjusting inputs of the second and third counters.

 The problem solved in the proposed device is to provide signal processing in the entire possible range of the probable width of their spectrum. The technical result achieved in this case is that continuous recording of digitized information from the output of the dispersion analyzer to the online recording node is performed. Using the first comparison node, the half value of the current information is compared with the information recorded in the memory node, and the code of the number characterizing the lower boundary frequency of the spectrum (determined by the section method of level 0.5) is generated in the first register according to the result of the comparison. Using the second comparison node, the moment is recorded when the current value of the digitized signal becomes less than 50% of its maximum value, that is, a code of a number characterizing the upper cutoff frequency of the spectrum is generated in the second register. After the generated information about the lower and upper boundaries of the spectrum is fixed in the recording unit, the RAM node and the registers are restored to their original state. As a result, the device is able to start processing the next signal, regardless of what the width of the previous processed response was.

 In FIG. 1 presents a structural diagram of the proposed device; in FIG. 2 timing diagrams explaining the operation of the device; in FIG. 3 is a structural diagram of a prototype device.

In FIG. 1 and 3, the following notation is accepted:
1 dispersive spectrum analyzer,
2 amplitude detector,
3-1, 3-2 1st and 2nd nodes of comparison,
4-1, 4-2 1st and 2nd pulse shapers,
5 synchronizer,
6-1, 6-2 1st and 2nd elements And,
7 analog to digital converter,
8 node RAM
9-1, 9-2 1st and 2nd registers,
10 recording unit,
11-1, 11-2, 11-3 and 1st, 2nd and 3rd counters,
12 multiplexer,
13 element delay
14 element OR,
15 source of logical unit potential,
In FIG. 2 adopted the following notation:
16 signal at the DAS sync input,
17 signal at the third output of the synchronizer,
18 signal at the second output of the synchronizer,
19 signal at the output of the amplitude detector,
20 signal at the output of the analog-to-digital converter,
21 signal at the output of the second element And,
22 signal at the output of the first element And,
23 signal at the output of the delay element.

In FIG. 3 adopted the following notation:
24 delay line,
25 second amplitude detector,
26 peak detector
27 voltage divider
28 time meter,
29 shift register
30 duration selector.

 The proposed device contains a series-connected dispersive spectrum analyzer 1 and amplitude detector 2, the analyzer input being the device input, the first 3-1 and second 3-2 comparison nodes, the first inputs of which are combined, the first 4-1 and second 4-2 pulse shapers, the inputs of which are combined, a synchronizer 5, the first output of which is connected to the sync input of block 1, and the second to the inputs of the drivers 4-1 and 4-2. The device also includes the first 6-1 and second 6-2 AND elements, serially connected analog-to-digital converter 7, a memory node 8 and a first register 9-1, as well as a second register 9-2, and the information input of block 7 is connected with the output of the amplitude detector 2, the sync input with the second output of the synchronizer 5, and the output with the first inputs of the comparison nodes 3-1 and 3-2, the input of the register 9-1 is connected to the second input of the node 3-1, and the output to the second input of the node 3- 2, the output of which is connected to the input of the element 6-1. The device also contains a recording unit 10, the first information input of which is connected to the output of the register 9-2, the second information input to the second output of the register 9-1, and the clock input to the output of the element 6-1, counters 11-1, 11-2 and 11- 3 and multiplexer 12. The output of the first counter 11-1 is connected to the second input of the memory node 8 and to the input of the register 9-2, the inputs of the multiplexer 12 are connected to the outputs of the counters 11-2 and 11-3, and the output is with the address input of the memory node 8, the recording input of which is connected to the output of the shaper 4-1, the input of which is connected to the counting input of the counter 11- 1 and the counting input of the counter 11-2, as well as with the address input of the multiplexer 12 and the second output of the synchronizer 5. The first input of the element 6-2 is connected to the output of the comparison node 3-1, and the second input is combined with the second input of the element 6-1 and the output shaper 4-2. The device also contains a delay element 13 and an OR element (14), the output of which is connected to the installation input of the register 9-1, the first input to the installation input of the counter 11-1 and the third output of the synchronizer 5, and the second input to the output of the delay element 13, the input of which is connected to the clock input of the register 9-2 and the output of the element 6-1. The second input of the register 9-1 is connected to the second output of the node 8, and the third to the source of the potential of the logical unit 15, the clock input to the counting input of the counter 11-3 and the output of the element 6-2, and the third output to the installation input of the counters 11-2 and 11- 3.

 The device operates as follows.

поэтому на выходе узла 3-1 формируется уровень логической единицы и подаются на первый вход элемента И (6-2).At the first output of the synchronizer 5 with a frequency that determines the cycle of the device, pulses are generated that are fed to the sync input of the dispersion analyzer 1 and start it (Fig. 2-16). Timing diagrams of FIG. 2 illustrate the operation of the device within one cycle. After some fixed time, a radio signal begins to act at the output of the dispersion analyzer, the envelope of which in time scale repeats the amplitude spectrum of the signal at the output of the device. A pulse appears at the third output of the synchronizer (Fig. 2-17), which corresponds to the point in time from which responses corresponding to spectral bursts begin to form (Fig. 2-19.2-23 show the operation of the device using one spectral burst as an example). This pulse sets the initial counter 11-1 (logical unit on all outputs) and register 9-1 (zeroing direct outputs). At the third (inverse) output of register 9-1, the level of the logical unit is set, so the counters 11-2 and 11-3 are also set to the initial state (logical zeros at all outputs). At the second output of the synchronizer 5, a sequence of clock pulses begins to form (Fig. 2-18). Under the control of these pulses, the analog-to-digital converter 7 encodes the signal from the output of the amplitude detector 2 (Fig. 2-19). At the output of converter 3, a sequence of digital numbers is formed, which is determined by the amplitude of the samples from the signal, which are conventionally shown in FIG. 2-20 in the form of vertical segments of the appropriate height. Clock pulses have the shape of a meander, that is, the duration of each individual pulse is equal to the interval between adjacent pulses (Fig. 2-18). For the duration of the clock pulse, the multiplexer 12 translates to the address input of the memory node 8 the state of the output bus of the counter 11-2. On the edge of the clock pulse to the contents of the counter 11-1 is added one. At the same time, a shaper 4-1 is launched along the edge of the clock pulse, the pulse from the output of which records information into the memory node 8. The amplitude of the sample is recorded at the first input of node 8, and the number of this sample (i.e., the value of the spectral frequency) determined by the state counter 11-1. In the interval between clock pulses, the multiplexer 12 translates to the address input of the memory node the state of the output bus of the counter 11-3. In this case, the state of the counters 11-2 and 11-3 are the same (zero), therefore, at the outputs of the memory node we have information corresponding to zero point 0 (Fig. 2-20, point 0): amplitude 0 (zero), time 0 (zero ) At node 3-1, half the amplitude of point 0 (input X) is compared with amplitude 0 (input Y) in accordance with the rule

therefore, at the output of node 3-1, the level of the logical unit is formed and fed to the first input of the And element (6-2).

для двух смежных информационных точек (в примере на фиг. 2-20 это точки с 0 до 5). Когда будет сравниваться половина амплитуды 6-й выборки с амплитудой 5-й выборки, импульс на выходе элемента 6-2 не сформируется, так как на выходе узла 3-1 установится логический нуль. Поэтому информация на выходе регистра 9-1 и состояние счетчика 11-3 не меняется и в следующем такте будет производиться сравнение половины амплитуды 7-й выборки с амплитудой 5-й выборки в рассматриваемом примере в регистр 9-11 будет записана информация о 5-й выборке. Процесс будет продолжаться до тех пор, пока в регистре 9-1 окажется записанной следующая информация: цифровой код о половине максимального значения отклика (для фиг. 2-20 соответствует амплитуде 8-й выборки) и номер этой выборки (здесь 8). Во всех тактах производится сравнение амплитуды входных выборок и информации с регистра 9-1. В тот момент, когда амплитуда входной выборки окажется меньше информации с первого выхода регистра, на выходе элемента И (6-1) формируется импульс, по фронту которого в регистр 9-2 записывается цифровой код, соответствующий времени окончания сигнала по уровню 0,5 (на фиг. 2-22 этот номер выборки 20). Этот же импульс поступает на сихровход регистрирующего блока 10 и по его срезу производится запись информации ее второго выхода регистра 9-1 (соответствует нижней граничной частоте f_н спектрального отклика) и с выхода регистра 9-2 (соответствует верхней граничной частоте f_в спектрального отклика). В блоке 10 эта информация преобразуется в необходимую форму для последующей обработки или визуализации (например, вычисляется средняя частота f_o=(f_н+f_в)/2 и ширина спектра Δf = f_в-f_н Кроме того, задержанный на некоторое время в элементе 13 импульс (фиг. 2-23) переводит в исходное состояние регистр 9-1, а через него и счетчики 11-2 и 11-3, то есть устройство оказывается подготовленным к обработке следующего сигнала.On the cut of the clock pulse, the shaper 4-2 is started, the pulse from the output of which is supplied to the second input of the element 6-2. In this example, an impulse appears at the output of element 6-2, the front of which information about the point) is recorded in register 9-1. The state of the counter 11-3 does not change, since at the moment of the front acting on the counting input, the state of its installation input has not yet changed. However, after passing through this front, the counters 11-2 and 11-3 are put into operation, since the potential of logical zero appears on the third output of register 9-1. In the timing diagram of FIG. 2-21 shows the pulses from the output of the element 6-2, which write information to the register 9-1. The numbers under these pulses indicate the number of that sample (Fig.2-20), information about which is recorded in the register of the corresponding pulses. On the front of the next clock pulse, the state of the counters 11-1 and 11-2 changes by one and information about point 1 is recorded in node 8 (Figs. 2-20). During the next time interval between clock pulses in node 3-1, the half amplitude of point 1 (input X) is compared with the amplitude of point 0 (input Y). In the example under consideration, an impulse appears at the output of element 6-2, the front of which contains information about point 1 in register 9-1. The process of continuous formation of pulses at the output of the element And (6-1) will continue until the condition

for two adjacent information points (in the example in Fig. 2-20 these are points from 0 to 5). When half the amplitude of the 6th sample is compared with the amplitude of the 5th sample, the pulse at the output of element 6-2 will not be formed, since a logic zero will be set at the output of node 3-1. Therefore, the information at the output of register 9-1 and the state of the counter 11-3 does not change, and in the next clock cycle, half the amplitude of the 7th sample will be compared with the amplitude of the 5th sample in this example, information on the 5th will be recorded in register 9-11 sampling. The process will continue until the following information is recorded in register 9-1: a digital code about half the maximum response value (for Fig. 2-20 corresponds to the amplitude of the 8th sample) and the number of this sample (here 8). In all clock cycles, the amplitude of the input samples and the information from register 9-1 are compared. At the moment when the amplitude of the input sample is less than the information from the first output of the register, an impulse is generated at the output of the And (6-1) element, along the edge of which a digital code is written in register 9-2, corresponding to the signal end time at the level of 0.5 ( in Fig. 2-22, this sample number 20). The same pulse is fed to the current input of the registering unit 10 and its information is recorded on its second output of the register 9-1 (corresponds to the lower cutoff frequency f _{n of the} spectral response) and from the output of the register 9-2 (corresponds to the upper cutoff frequency f _{in the} spectral response) . In block 10, this information is converted into the necessary form for subsequent processing or visualization (e.g., calculates the average frequency f _o = (f _n + f _c) / 2 and a spectral width Δf = f _n -f _in addition, delayed by a time in element 13, the pulse (Fig. 2-23) transfers the register 9-1 to its initial state, and through it the counters 11-2 and 11-3, that is, the device is prepared for processing the next signal.

 The proposed device allows you to process multi-frequency spectral information without omissions, regardless of the probable width of individual spectral responses, the frequency interval between them and the amplitude of each of them.

Claims (1)

 A spectral parameter meter of radio signals containing a dispersion spectrum analyzer, an analog-to-digital converter and a synchronizer, the first and second outputs of which are connected respectively to the sync inputs of the dispersion analyzer and an analog-to-digital converter, characterized in that an amplitude detector is inserted into it, connected in series with a dispersive spectrum analyzer , the input of which is the input of the device, the first and second nodes of comparison, the first inputs of which are combined, the element And, as well as l of RAM and a recorder connected in series with the analog-to-digital converter, the information input of the analog-to-digital converter connected to the output of the amplitude detector, and the output with the first inputs of the comparison nodes, the register input connected to the second input of the first comparison node, and the output to the second input the second comparison node, the output of which is connected to the input of the AND element, the recording unit, the second register, the output of which is connected to the information input of the recording unit, the second information input One of which is connected to the second output of the first register, and a clock input with the output of the And element, the first counter, the output of which is connected to the second input of the RAM node and the input of the second register, the second and third counters, a multiplexer, the inputs of which are connected to the outputs of the second and third counters, and the output with the address input of the memory node, the recording input of which is connected to the output of the first driver, the input of which is connected to the counting inputs of the first and second counters, as well as to the address input of the multiplexer, the input of the second synchron jam, the second AND element, the first input of which is connected to the output of the first comparison node, and the second input is combined with the second input of the first AND element and the output of the second driver, the delay element and the OR element, the output of which is connected to the installation input of the first register, the first input to the installation the input of the first counter and the third output of the synchronizer, and the second input to the output of the delay element, the input of which is connected to the clock input of the second register and the output of the first element AND, the second input of the first register is connected to the second ode node memory, a third input to the source logical unit capacity, the clock to the count input of the third counter and the output of the second AND gate and the third output - to the installation of the second and third inputs of the counters.

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