SU677097A1 - Analogue-digital reading-out converter - Google Patents

Description

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The invention relates to digital measuring and computing technology and can be used in digital measuring installations and systems for digital measurement (coding) of voltage signals in a wide range of their level and spectrum.

A parallel-to-digital-to-digital converter (ADC) is known with a parallel propagation of the signal. It contains a series of comparison stages — coded and reference voltage comparators, each of which generates a weight current for adjacent lower-order stages, proportional to the difference of the compared signals. The weight currents are converted by special elements into reference voltages.

A disadvantage of this device is the reduced speed in expanding the range of levels of the measured value, since this requires additional time for analysis and selection of the measurement limit.

Closest to the invention, according to the technical nature of the ADC, contains a series of coding, and their cascades, each of which includes a group of parallel-connected measuring comparators, work according to the reading method, and the cascades themselves are connected to each other in series 2.

The disadvantage of this device also relates to a decrease in its speed with

expansion of the range of levels of the measured value. In addition, with an increase in the number of quantization levels of sushi; the number of code-to-voltage converters in each given cascade, forming a reference voltage for individual comparators in this cascade, increases in accordance with the size of the output code of the previous cascade.

The purpose of the invention is to increase the speed of the device in a wide range of levels of the measured value.

The goal is achieved by the fact that, in an analog-to-digital read converter, containing a group of decades of measuring comparators, the measuring inputs of which are connected in parallel and connected to the input terminal of the device, the unit-to-voltage converters connected in series

clock generator, code register and data accumulation and display unit, connected to the clock generator and code register, a scale divider is inserted, included

between the input terminal and the common bus,

large-scale comparators, each of which is connected by a measuring input to a corresponding scale-divider voltage source, an exemplary signal source, a key element connected by corresponding inputs to a clock generator and an exemplary signal source, and an output to the reference input of each large-scale comparator, a digital-analog reference voltage source, to each of the inputs of which is connected by its output a corresponding large-scale comparator, a decade divider connected between the output of the digital-to-digital channel the primary source of the reference voltage, to which the first of the series-connected converters of the unit code to the voltage is also connected, and the common bus, bypassing the key elements and decimal dividers. Each of the decimal dividers is connected between the output of the corresponding converter of a single code to voltage and a common bus, decades of measuring comparators are connected to the steps of the ten-day dividers and shunt key elements are connected to parts of the steps of each of the decimal dividers. . The inputs of the shunt key elements of the corresponding stages of decimal dividers are connected in parallel with each other, as well as with the inputs of the corresponding converters of the unit code to the voltage and the outputs of the measuring comparators of the corresponding decades. The outputs of one of the decades of measuring comparators of} 1 are connected to the code register, which is also connected to the code outputs of converters of a single code into a voltage and a digital-analogue source of the reference voltage.

Functional diagram of the device shown in the drawing.

It contains the input terminal 1 of the device, steps 2 of the large-scale divider, large-scale comparators 3, key element 4, source 5 of the reference signal; b clock generator; digital to analogue source 7 reference voltage; steps 8 decade divider ,, decade 9 comparators (high decade), unit code to voltage converter 10 (PEKN of the highest decade) with input AND reference voltage, shunt key elements 12, steps 13, 14 (R and 10-) dec partial divider, decade 15 comparators (second decade), unit code 16 to voltage converter, steps 17-19 (R, 10-R and IQ-R) decimal divider, decade 20 comparators (third decade), unit code converter 21 in voltage, steps 22-25 (R, 10-R, ...,, 10 - (- 1) R) decimal divider, decade 26 comparators (younger th decade), code register 27 s

the inputs 28 of the code signals (p-1) of the highest decades and the limit of the measured value, the block 29 of accumulation and display of data with the input 30 of the code read signals, the common bus 31. The position 32 in the drawing denotes the code output of the digital-analogue source 7, and the position 33 output PEKN.

The device works as follows.

The measured (coded) value U, arriving at input terminal 1, is transmitted directly to the comparators of all decades 9, 15, 20, ..., 26, and through the steps 2 of the scale divider simultaneously to the scale comparators 3. The number of steps of the scale divider choose based on the required number of measurement limits, and the ratio of the values of the steps - in accordance with the value of the lower limit.

The signal of the generator 6 clock pulses through gated key element 4 to the reference input of all large-scale comparators 3 is applied the voltage of the source 5 of the sample signal, equal to the youngest limit of measurements. The measured value is distributed along the scale comparators 3 in accordance with the steps 2 of the divider, decreasing in the direction of the scale comparator of the largest of the limits connected to the last step of the scale divider. Since in the device operations are performed with a decimal positional (parallel unit) code, it is advisable to choose the steps of the scale divider equal to R, IOR, 102, ..., where k is the number of measurement limits, which is a natphalic series.

When comparing the measured voltage Ux- with the reference voltage of the source 5, part of the scale comparators 3, in accordance with the limit of the measured value, triggers and switches the digital-analogue source 7 of the reference voltage in such a way that the voltage Uap equal to the limit of the measured value. The voltage f / np, distributed by steps 8 of the decade divider equal to R, over the comparators of decade 9 and compared with the measured one. The voltage level of each stage of the decade divider differs from the next by a quantum 0.1 C / Ave. When comparing the voltage / x in the comparators of the decade 9c, the voltage f / np, the part of the comparators works, their number is equal to the value Ki of the highest decimal digit of the measured value, where / Ci l, 2, ..., 9.

A parallel unit code of the highest decade, equal to ki, is transmitted to the converter 10 of the unit code to the voltage of the highest decade, the reference voltage of which is Um), the output voltage of the digital-analog source 7, and is converted to f / on voltage. S О Л f / np + (О,) - t / ,, p (k, + l)., Where (0,1 f / пр) is the initial one. the output voltage level of the PEKN 10. Thus, the voltage Uon is equal to the value of the measured voltage, rounded to the nearest integer value of the high-order bit (i-H) .lO-i C / pr. All converters 10, 16, 21 are one-decade, with the decade steps of each PEKN of the lower order being reduced by an order of magnitude compared to the PEKN stages of the previous most significant bit. The output voltage of the PEKN of each previous decade is the reference for the PEKN of the subsequent lower decade. A decimal divider is connected to the output of the PEKN each decade, to a number of steps of which (a decade of steps) decades of measuring comparators are connected to its reference input. Such groups of decades 15, 20 ..., 26 comparators, together with a group of 9 comparators, contain only the ADC in the number of decimal places of the lower limit of measurements. The first group of 9 comparators, as mentioned, forms the signals of the code of the highest decade and is connected to the decimal divider with the steps R (8). The second group 15 of comparators generates signals of the code of the second highest decade and is connected to a decimal divider with steps that are an order of magnitude smaller and equal to 10 R (14). The comparators of the nth group, which form the signals of the lower decade code, are connected to the steps (R) of the corresponding decimal divider. Each of the decade steps from 10-R to IQ- (n-i) f with connected measuring comparators is, in turn, a discretized level (with the indicated discrete step) of the corresponding neighboring higher-than-nominal value of this decimal divider. In this case, the first of p-1 decimal dividers contains 9 successive stages 13 through J, each of which is connected in parallel with a shunt key element 12, and a decade discrete stage 14 with schagam 10R. The second decimal divider contains 9 levels 17 through and 9 steps 18 along R, shunted by key elements 12, and a discretized step 19 with a step of 10 R, and the last decimal divider, at the output of PEKN 21 of the penultimate lower decade of the code, has consecutive chains of 9 consecutively connected steps R (22), 10 -1 R (23) 10 - (- 2) R (24), also shunted by key elements 12, and a decade discretized step in increments of 10 - (- 1) R (25). In the initial state, all shunt key elements 12 are closed. The key elements 12 connected to the stages of one nominal decimal dividers are connected in parallel by their directing inputs to the outputs of the corresponding measuring comparators in circuits of discretized stages of the same rating, i.e. the key elements of the 12 steps R - 13, 17, 22 of all decimal dividers are connected in parallel to the comparators (9) in the chains of the corresponding steps R (8) of the ten-day divider, the key elements of the 12 steps 10 R (23) of all decimal dividers are to the comparators (15) of the corresponding steps of the decimal divider at the output of PEKN 10, up to the key elements of the steps 10 (-) R. At the output of every 1st PEKN, where r 1,2, ..., (p-I), the measurement process sequentially sets the voltage OP, (, 1) - 10 - (, +) X lO-f / np, (0 each of which is equal to the measured, increased at the level of e of the 1st bit to its nearest larger integer value equal to (/ C, + 1) (UnpKi - the decimal bit code of the gth decade can take values from I to 9). The indicated increase in the decade is provided by presetting the corresponding the initial output level of each PEKN. The voltage at the output of the i-th PEKN is set by the signals of the measuring comparators of the corresponding group. The same elements unlock the key elements 12 associated with these comparators and thereby unlock the corresponding steps of the decimal dividers. The number of open nominal steps from R to 10 - (- R in the decimal divider connected to the PEKN output of the i-th decade turns out to be ki, k, ..., ki, ... Ji, respectively (due to which the voltage The output of the f-ro PEKN is distributed to the steps of the decimal divider connected to it always with a constant increment at each step (relative to the next), equal to t / np at step R, t / np-10-2 at step lO-i R , f / pr Young stage, and at the discretized stage divider with step lQ- R, the increment by the discrete is f / np 10 (. At discrete stage 25 with nominal) The value is equal to the f / np-lO-5 quantum, that is, the unit of the youngest decade of the code.

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Thus, due to the random adjustment (adaptation) of decimal dividers to the value of the measured value, the constant level at the input of each measuring comparator is proportional to the quantum and equal to the unit weight of the code of the corresponding decade. This allows (bit by bit) parallel comparison in each bit of a set of signals from a decade of constant reference levels with a level corresponding to the value of the given decimal place (decade) of the measured value. The formation of a set of reference levels for each decade divider with measurement comparators occurs sequentially in time with an interval equal to the switching time of the PEKN of the previous decade.

The output of PEKN 21 is set to a voltage equal to that measured to the penultimate decade, while the comparators (26) form the number of signals — the code corresponding to the value of the younger decade of the measured value. This code, together with the code signals, input 28 of the register 27), corresponding to the limit of the measured value (source code output 7) and the values n-1 of its most significant bits (code outputs PEKN 10, 16, 21) at the command of the generator b register 27 is transmitted to block 29.

In the proposed device, as compared with the prototype, the speed is increased in a wide range of changes in the levels of the measured quantity and spectrum.

Claims (2)

1. USSR author's certificate number 226975, cl. H OZK 13/03, 1968. 2. E. Gitis. Information converters for electronic digital computing devices. M., “Energie, 1975, p. 316-320, fig. 7-11 b, c.