SU668084A1 - Multichannel converter - Google Patents

Multichannel converter

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Publication number
SU668084A1
SU668084A1 SU762315958A SU2315958A SU668084A1 SU 668084 A1 SU668084 A1 SU 668084A1 SU 762315958 A SU762315958 A SU 762315958A SU 2315958 A SU2315958 A SU 2315958A SU 668084 A1 SU668084 A1 SU 668084A1
Authority
SU
USSR - Soviet Union
Prior art keywords
counter
input
bits
computer
voltage
Prior art date
Application number
SU762315958A
Other languages
Russian (ru)
Inventor
Тельман Аббас Алиев
Намик Сулейман Алиев
Original Assignee
Институт Кибернетики Академии Наук Азербайджанской Сср
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Институт Кибернетики Академии Наук Азербайджанской Сср filed Critical Институт Кибернетики Академии Наук Азербайджанской Сср
Priority to SU762315958A priority Critical patent/SU668084A1/en
Application granted granted Critical
Publication of SU668084A1 publication Critical patent/SU668084A1/en

Links

Description

(54) MULTICHANNEL TRANSMITTER
This invention relates to a measurement technique. The device can be used to convert multi-channel analog signals into a digital code and input them into an electronic computing machine (computer).
A multichannel servo-type transducer is known, containing a reversible counter, a source of linear-step compensating voltage, comparing device, pulse generator 1. However, when building multi-channel transducers based on this principle, the complexity of the equipment increases in proportion to the number of input channels. This practically leads to the fact that m single-channel transducers are required to convert analog signals received from m sensors.
Closest to the offer is a multichannel converter containing pulse counters connected via a key to a pulse generator and individual comparison blocks in each of the channels with connecting the outputs of each of the comparison blocks through individual buses to the computer for issuing the address portion of the readable code 2.
At each step of converting such a converter, when a digital value of the analog signal of each channel is transmitted to a computer, it becomes necessary to send a separate signal to a computer that indicates which input channel of the converter is input to a computer. And the information transmitted by the E computer for each of. these communication lines in each step, before ordering the transformed information along the input channels, must be remembered, which leads to unjustified loading of computer memory with redundant information. In addition, in the indicated device in each conversion stage, for each input channel, a binary code is determined and transmitted to the computer, the bit of which is equal to the counter size of the code-to-voltage converter. These binary codes contain redundant information, which ultimately also leads to redundancy of information encoded and transmitted to the computer.
The aim of the invention is to reduce the redundancy of information.
This goal is achieved in that a multi-channel converter containing a pulse generator, a key, a pulse counter, a code-to-voltage converter, comparison blocks, a one-shot, a register and a key group are entered, the output of each comparison block through the corresponding groups of keys is connected to the inputs the corresponding bits of the register, the information inputs of the key groups are connected to the outputs of the corresponding lower bits of the pulse counter.
Structural. the electrical circuit of the device is shown in the drawing.
The device contains a pulse generator 1, a switch 2, a pulse counter 3, a code-voltage converter 4, input channels 5 | -5m, comparison blocks .61-6m, register 7, groups of keys, one-shot 9.
The device works as follows.
At the beginning of each conversion step, at the output of the one-shot 9, a voltage permitting voltage is formed, which passes the pulses of the generator 1 through the key 2 to the input of the counter 3. With the arrival of each of these pulses, the contents of the counter increase by one. Due to this, the output of converter 4 forms a linearly-step voltage, the height of each step of which is equal to the weight of the younger discharge of counter 3. The number of digits in the counter is chosen so that the sum of the maximum number of steps of the specified voltage compared to the maximum possible range of input voltages signals would be more ..
With an increase in the content of counter 3 on blocks 6i-6m, the indicated stepped voltage is compared with all the input analog signals that are fed through the input channels. At the moment of equality of the analog signal of the j-th input channel to a step voltage at the output of the block 6), a pulse is generated. At this moment, the contents of the counter correspond to the binary code of the digital value. the analog signal of channel 5j and the indicated pulse through a group of keys 8J connected to the output of block 6j transfers the contents of the lower bits of the counter to those bits of register 7 whose inputs are connected to the outputs of groups of keys 8J. As a result, the n bits of the binary code of the analog signal of channel 5j are stored in the corresponding bits of the register.
Until the discharge grid of the counter overflows, 3 at the outputs of the blocks when the input signals of the corresponding channels are equal
 linear step voltage signals that, through the corresponding groups of Bi-8m keys, transfer the contents of the lower bits of the counter to the corresponding bits of the register 7. If two or more input analog signals coincide with the step voltage, the outputs of the comparison blocks of the corresponding channels through the corresponding groups of keys, the contents of the lower bits of the counter are transferred in parallel to the corresponding register bits.
At the moment of overflow of the discharge grid of the counter 3, the current step of converting the input signals into a digital code ends. From overfilling the discharge grid of the counter, it is reset to zero, and at the output of its most significant bit, a signal is generated that transfers the contents of register 7 to the computer. This signal also triggers the one-shot 9, at its output a time-prohibiting voltage level appears at the time i D t, which locks key 2 and stops the pulse from the generator 1 to counter 3.
Thus, during a single conversion cycle, the low-order bits of the binary codes transmit digital values of all input analog signals to the computer. In this case, it is not necessary to transfer to the computer the numbers of each channel along individual lines of communication, since at the end of the current device operation the results of the conversion of each channel are located in the corresponding register bits in a strictly defined sequence.
The next transformation step begins after the expiration of a time interval equal to the quantization step in time G D t. At the same time, at the output of the one-shot 9 the resolution level appears again, which allows the flow of the generator 1 pulses through the key 2 to the input of the counter 3. The next conversion cycle begins in the device, which proceeds as described above.

Claims (2)

1. Temnikov F. Ye. Theoretical foundations of information technology, M., Energie, 1971, p. 114, fig. 318.,
2. USSR author's certificate number 153399, cl. H 03 K 13/20, 1962.
SU762315958A 1976-01-16 1976-01-16 Multichannel converter SU668084A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
SU762315958A SU668084A1 (en) 1976-01-16 1976-01-16 Multichannel converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SU762315958A SU668084A1 (en) 1976-01-16 1976-01-16 Multichannel converter

Publications (1)

Publication Number Publication Date
SU668084A1 true SU668084A1 (en) 1979-06-15

Family

ID=20646163

Family Applications (1)

Application Number Title Priority Date Filing Date
SU762315958A SU668084A1 (en) 1976-01-16 1976-01-16 Multichannel converter

Country Status (1)

Country Link
SU (1) SU668084A1 (en)

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