SU728222A1 - Voltage-to-code convertor - Google Patents

Description

The invention relates to digital measuring and computing equipment and can be used in digital measuring installations and systems for digital measurement (coding) of voltage signals in a wide range of their level and spectrum.

A known voltage-to-code converter (PNA) of parallel reading with bitwise signal propagation, which contains a number of cascades of comparison — comparators of the encoded and reference (reference) voltages, each of which generates a weight current for neighboring cascades of lower-order discharges. dv proportional to the difference of the compared signals. Weight currents are converted by special elements into reference voltages [1].

A disadvantage of the device is a decrease in its speed when expanding the measurement limits by the level of the measured value, since this requires additional time for analysis and selection of the limit.

Known converter _; voltage to a code containing AND groups of gated comparators, measuring inputs of ^{5 of which are} connected to the input terminal of the device, where And is the number of decimal digits (decades) of the converted value, a converter consisting of decoding blocks connected in series, control unit and trigger registers, reset the inputs of which are connected to the reset input of the control unit, and the information inputs to the outputs of the gated comparators [2J.

The disadvantage of this device is the presence of a large number of code to voltage converters in the cascade, each of which forms a reference voltage for a separate comparator of this cascade. In addition, with the expansion of the operating range of the levels of the measured value, the performance of the device decreases, since an additional is required. " new. time to select the measurement limit.

The aim of the invention is to increase the speed of signal conversion in a wide range of changes in their level.

To do this, a voltage converter in code containing h groups of gated comparators, a converter, a control unit, and trigger registers are introduced. input divider of the converted value; gated input comparators *, divider, reference constant signal source, digital-to- ¹ lot source of maximum reference conversion voltages, key elements, AND elements, controllable decade dividers with R,. ”steps. 1O ~ ^and ~ ² ^ R, 1O ~ flip-flops, shifter of paired shifted pulses, a separate shaper of paired shifted pulses, the input of the input divider of the converted value being connected to the input terminal of the device, and the inputs connected to the measuring inputs of the gated input comparators alternator, the gate and reference inputs of which are connected respectively to the reset output of the control unit and to the output of an exemplary source of constant ιό signal, and the outputs are connected to the inputs of the digital-analog source of limiting 'exemplary voltages, the output of which is connected to the input voltage bus of the converter, the controlled decade dividers are connected afterwards tion with the inverter output, pri- than stage R, 10 ^{_ '1} R, ... 10''^ ^h "^ R ² ten-day controlled divisors shunted key elements, and outputs driving Mykh decadal dividers connected to -Log gated ^comparator: tori outputs of each flip-flop, except for the flip-flop younger decades, via AND-NO elements are connected to the inputs of the decoding key elements and the converter inputs, logic inputs Q-Nyo elements connected to the outputs of flip-flops the reset inputs of which are connected to the reset output of the control unit, the first output, the output of each shifter of paired shifted pulses is connected to the gate inputs of the gated comparators, the second output is connected yong to the input start trigger and to an input of driver pair shifted Pulses more junior decade code, and input of the pair | GOVERNMENTAL shifted pulse code older decade connected to a control output control unit Kotorpre entrance from & di "it with the first output of the individual generator paired shifted pulses ,.

_{5, the} second output of which is connected to the gating inputs of the gated computer, the radiators of the lower decade of the code, and the input is connected to the output of the shaper of the paired shifted pulses of the last but one of the last decade of the code. _f

The drawing shows a structural electrical diagram of the device. ;

The device comprises an input terminal 1 of the device; convertible input divider 2; gated comparators 3 input divider; control unit 4; reference constant signal source 5; digital-analog source of 6 ultimate reference voltages; a converter 7 of a parallel unit code into an exemplary reference voltage; decoding units 8, 9 of converter 7, respectively, from the oldest to the penultimate junior deck ²⁵ ; input bus. 10 reference voltages; key elements 11; controlled decade dividers 12, 13, 14 ', respectively, with steps Κ,.,. ^ ^- ^' ^ R, ΐό ^ Η ?; gated comparators of the 15-forming ³ θ code of the senior decade; gate, my comparators 16,17 are code generators, respectively, of the penultimate junior and 'junior decades; trigger register 18 high decade of code; logical ³⁵ elements AND 19; trigger 20 ;, shaper 21 paired shifted pulses; trigger registers 22, 23, respectively, of the penultimate junior and younger decades of the code; generates ⁴⁰ separate Vatel 24 paired shifted pulses;

common bus 25, -. .

The device operates as follows.

The converted (encoded) value ⁴⁵ supplied to the input terminal 1 is transmitted directly. To the measuring inputs of all gated comparators 14, 15, 16, and through the steps of the input divider 2 simultaneously to the strobe ⁵⁰ eMy comparators 3. The number of stages of the input divider is selected based on ; the required number of measurement limits, and the ratio of the values of the steps in accordance with the value of the lower ⁵⁵ limit.

The reference voltage of all gated comparators 3 is supplied with the reference voltage of the reference source 5 equal to '’· -' '· ~ · Τ · <Ί *. ·

728222 to 6 the lower limit of measurements. The measured value is distributed among the gated comparators 3 in accordance with the steps of the input divider 2, decreasing in the direction of the gated comparator _{5 of the} largest of. limits connected to the last stage of the input divider 2. Since the operation in the device is performed with a decimal positional '(parallel unit) code, then the steps 10 of the input divider are selected equal. R, 1OR ,: lO ^ R., 10 * 1 ?, where k is the number of measurement limits; representing a natural number.

When comparing the measured voltage ¹⁵ with the reference one in the gated comparators 3, some of them will work in accordance with the limit of the measured value and switch the digital-analog source 6 so that at its output ²⁰ the ICR voltage equal to the limit of the measured value appears. This voltage is supplied as a reference voltage to input 10 of converter 7. The described operation cycle is performed in accordance with ²⁵ <with the gating signal generated in block 4, which is transmitted to the corresponding input of the gated Comparators 3. The same signal. Elements and the whole device! are set (reset- ³⁰ ) in the initial state.

To the output of the converter 7 are connected controlled ten-day dividers 12, '13, 14, which contain respectively '9 steps.!?, 9 steps, ³⁵

R-lcH 9 steps R-IO '^^ _and 10 steps 1?> 10 ~. In the initial state, all key elements 11 are open, the resistance of the controlled decade dividers 12, 13, 14 is maximum. ⁴⁰ and at the output of the converter 7, the voltage is equal to the selected limit, which is distributed in a constant increment.

According to the signal received from block 4 ⁴⁵ to the driver 21, a gating pulse of the gated comparators 15 is generated, and some of them, in accordance with the value (K ^ = 1 ... 9) - the highest digit of the measured value code, will work and switch connected to This is the trigger register 18 of the highest bit of the code. · With the delay required for triggering the gated comparators _$$ torors 15 and switching the trigger register 18, a second pulse is generated in the driver 21. This pulse (switches trigger 20, the output signal of which goes to a group of AND-NOT 19 elements connected to trigger register 18. At the same time, signals that will include the corresponding the key elements 11 and switch the decoding unit 8. At the output of the converter 7, the voltage ϋ _{0Πζ (} equal to the convertible code rounded at the highest level of the code of the converted value to the nearest larger integer value is set.

The second delayed pulse generated in the driver 21 is transmitted to a similar driver 21 in the gating circuit of the gated comparators 16 of the next divider stages equal to 0.1 R (not indicated in the drawing). A code K is _generated which is stored in the corresponding trigger register, and the reference voltage U _{on <} changes to and _0П2 , equal to the measured, rounded. At the level of the second decimal place of the converted value to the nearest larger integer value. Next, the process of generating codes is repeated. As the codes K j and voltages are generated, the corresponding steps of the controlled decade dividers 12, 13 are disconnected (shunted), thanks to which the voltage increment at each unshunted step and the gated comparator connected to it all the time remains unchanged.

After the code is generated, the voltage And _op (and-4) will be established at the output of the converter 7 · a gating pulse of gated comparators 17 will be generated ^{in the} corresponding separate shaper 24, which will give the code κ, γ] of the younger decade. This code is recorded in the trigger register 23 of the junior decade of the code. Thereby, a gating impulse of the gated comparators 17 will be generated, which will give out the code k to the younger decade. This code will be recorded in the trigger register 23 of the younger decade of the code. This will complete the cycle of the conversion of the input quantity, about which the corresponding driver 24 signals the unit

4. The bits of the code for this signal can be read from the trigger registers 18 ..... 22, 23 (the read chains are not shown in the drawing), after which the control unit resets all triggers

723222 ger converter to the initial state, and the coding cycle is repeated.

Together with the code, the coded value of this transformed voltage limit is also read from block 6.

Thus, the device provides bitwise adjustment of the steps of the controlled decade divider and the output voltage in accordance with the value of the converted voltage in; wide range of levels.

Claims (2)

The invention relates to digital measuring and computing technology and can be used in digital measuring installations and systems for digital measurement (coding) of voltage signals in a wide range of their level and spectrum. A known voltage transformer in code (PNK) of parallel coupling with random propagation of a signal, which contains a series of comparison stages —comparators of coded and exemplary (normal) voltages, each of which generates a weight current for neighboring stages of lower-order bits. proportional to the difference of the compared signals. The weight currents are transformed with special elements into reference voltages | l. The disadvantage of the device is a decrease in its speed when extending the measurement limits by the level of the measured value, since it requires additional time for analysis and selection of the limit. The converter is known; the voltage into the code containing AND groups of gated comparators, the measuring inputs of which are connected to the input terminal of the device, where h is the number of dec. tfflix bits (decade) of the value being converted, a converter consisting of serially connected decoding blocks, a control unit and trigger registers, the fault inputs of which are connected to the reset input of the control unit, and in () the gates of the comparators 2. Disadvantage device is the presence of a large number of code-to-voltage transducers in a cascade, each of which forms a reference voltage for a separate comparator of a given cascade. In addition, when extending the operating range The performance of the device is reduced at the levels of the measured value, since it requires a full-time time to select the measurement limit. The invention of the invention is a repetition of the speeds of the signals in a wide range of variations in their level. Operating comparators, converter, control unit, P trigger register, input divider of transformable value entered; strobe comparators of the input, divider, exemplary IS, constant signal switch, digital-analogous source of ultimate reference conversion voltages, key elements, elements, controlled dekad1-1 dividers with steps R, ..,,. the triggers, a forger of paired shifted pulses, a separate napraix shifter of shifts for pulses, the input divider of the converted quantity is connected to the input terminal and the device, and the inputs are connected to the measuring inputs of the gated comparators of the input de. A gate whose gating and reference inputs are connected respectively to the reset output of the control unit and to the output of the reference source of a constant signal, and the outputs are connected to the inputs of the digital-to-analog source of limit reference circuits, the output of which is connected to the input busbar of the voltage of the converter voltage, controlled by decade dividers are connected to the latter, with the output of the converter, with-. than the steps R,, ... of controlled decadal dividers are shunted by key elements, and the codes of controlled decadal dividers are controlled by inputs of gated comparators, outputs of the thriller register with the exception of the triggered register of the lower decade, and the elements of AND-NOT connected to the inputs {b of oche elements and the decoder with the inputs of the transducer, the popagic inputs of the elements of the--Ё are connected to the outputs of the flip-flops, the reset inputs / of which are connected to the exit terminal of the control unit, the first output of each terminal pair These pulses are connected to the gate inputs of the gated comparator. The second output is connected to the trigger start input and to the input of the paired shifted shifter of the younger decade of the code, and the input of the paired shifter of the higher decade of the code is connected to the control output of the control unit, Kot.K. ; djen with the first output of a separate paired shifted pulse generator, the second output of which is connected to the gate inputs. strobing D4x comparators of the junior decade of the code, and the input ene with the output of the shifter of the shifted pulses of the penultimate minor de1 {hells of the code “. The drawing shows a structural electrical circuit of the device .; The device contains an input terminal 1 of the device; input divider 2 convertible value; gated comparators 3 input divider; control unit 4; exemplary constant source 5; digital-analogue source 6 limit values: transform conversion voltages; converter 7 parallel unit-of-code into exemplary reference voltage; decoding blocks 8, 9 of converter 7, respectively, from: senior to the penultimate lower decade; input bus. 10 support stress; key elements 11; controlled decadal dividers 12, 13, 14, respectively, with steps; gated comparators; 15 generators of the high decade code; gated compressors 16,17 - code generators, respectively, of the penultimate younger and younger decades; trigger register 18 of the highest decade of the code; logical elements AND NOT 19; trigger 20 "shaper 21 paired shifted pulses; triggers registers 22, 23, respectively. of the preceding junior and junior decade code; separate shaper 24 guys x CiDiivytyty pulses; common bus 25.-. -. The device works as follows. The value convertible (coded) arriving at input terminal 1 is transmitted directly to the measurement inputs of all gated comparators 14, 15, 16, and through the input divider 2 steps simultaneously to gate 1 Comparators 3. The number of steps INPUT1X) divider is chosen based on; the required number of measurement limits, and the ratio of the magnitudes of the steps in accordance with the value of junior) tfedela. The reference, the input of all gated commutators 3, is supplied with the reference voltage of the exemplary source 5, equal to the youngest limit of the measurements. The measured video is distributed by gated comparators 3 in accordance with the steps of the input divider 2, decreasing in the direction of the gated comparator of the largest of. limits connected to the last step of the input divider 2. Since the operations in the device are executed with the decimal positional (parallel unit) code, the steps of the input divider are chosen equal to R, 101 ,:: .. ..,, where k is the number of limits measurements; representing a natural series. When comparing the measured voltage with the reference in the gated comparators, 3 of them, in accordance with the limit of the measured value, work and switch the digital-analogue source 6 in such a way that , is equal to the limit of the measured value. This voltage as a reference is supplied to the input 10 of the converter 7. The described clock cycle is performed in accordance with the gating signal generated in block 4, which is transmitted to the cooTV corresponding input of gated icoMnaptors 3. With the same signal, the elements and the entire device are set ( reset) to its original state. To the output of the converter 7, controllable decadal dividers 12 13, 14 are connected, which contain the corresponding 9 stages, 9 stages, R-10 -, ..., 9 stages R-IO and 10 stages R10. In the initial state, all the key elements of 11 pts are covered, the resistance of the controlled decade dividers 12, 13, 14 is maximum and at the output of the converter 7 the voltage is equal to the selected limit, which is distributed in constant increment. i The signal received from block 4 to shaper 21 generates a gating impulse of gated comparators 15, and some of them, in accordance with the value of K (K 1 ... 9) - the highlight of the code of the measured quantity will work and switch the connected K. Splash trigger register IS of the most significant bit of a code. With a delay necessary for the gating comparators 15 to operate and the trigger register 18 to switch, the second pulse is formed in the former 21. This pulse switches the trigger 2O, the output signal of which is fed to a group of NE-NE 19 connectors to the trigger register 18. At the same time, the output of the IS-NOT 19 elements in the circuit of the triggered comparators 15 that do not involve TC signals will turn on correspondingly. The key elements 11 and switch the decoding unit 8. On the converter 7, a voltage UQ will be set, equal to the transformed rounded at the level of the most significant bit of the code of the value being converted up to the shortest larger integer value. The second delayed pulse formed in the former 21 is transmitted to a similar former 21 in the gating circuit of the gated comparators 16 of the next divider levels equal to O, 1 R (not indicated in the drawing). A code K ,, which is stored in the corresponding trigger register is generated, and a reference voltage (J changes to and on 2 measurable, rounded At the second decimal level of the converted value to the nearest most large integer value. Next, the process of forming the repeat codes As the code 6k is generated and the voltages are turned off (bypassed), the corresponding stages of controlled decadal dividers 12, 13, thanks to which the voltage increment on the -unted stage and the gated computer connected to it The ramometer remains unchanged all the time. After forming the K code, the output of the converter 7 is set to tense and op (n - i) - a gating pulse of the gated comparators 17 will be generated by the corresponding separate driver 24. This code will be written in the trigger register of the 23 youngest decade of the code. This will generate a gating impulse for the gated comparators 17, which will issue the code of the younger decade. This code will be written in the trigger register of the 23 youngest decade of the code. This will complete the conversion cycle of the input value, which the corresponding driver 24 signals to block 4. The code bits on this signal can be read from the trigger registers 18 22, 23 (the reading circuits in the drawing are not indicated), after which the control unit resets everything the triggers of converter B are outgoing, and the coding cycle is repeated. Together with the code from block 6, the coded value of this limit of the transformed voltage is read. Thus, the device provides the memory of one stage of the controllable decadal divider and output voltage in accordance with the value of the voltage being converted to; wide range of levels. Claims of the voltage converter in the code containing AND groups of gated comparators, the measurement inputs of which are connected to the input terminal of the device, where h is the number of decimal places of the converted quantity, the converter consisting of sequentially connected decoding blocks, a control unit, and AND trigger registers, the fault inputs of which are connected to the reset output of the control unit, and the information inputs to the outputs of gated comparators, which, in order to increase growth of conversions in a wide range of changes in their level, input divider of the transformed value, gated input comparators of the divider, an exemplary constant signal source, a digital-to-analog source of limiting exemplary transforming voltages (transients, key elements, AND-NOT controls, introduced decadal dividers with steps. R, ... R, I, triggers, paired shifter shaper, a separate paired shifter shaper, and the input of the input divider with the input terminal of the device, and the outputs are connected to the measuring inputs of the gated comparators of the input divider, the gating and) where the inputs are connected respectively to the reset output of the control unit and to the output of the exemplary constant signal source, and the outputs are connected to the inputs of the digital-analog source of the limit sample the SRI, the output of which is connected to the input bus of the reference voltage, is transformed. solids, controlled decade dividers are connected in series with the output of the converter, the steps R, 10-R. controlled de-slotted dividers are shunted with the walk-through elements, and the outputs of the controlled decade dividers are connected to the inputs of gated comparators, the outputs of each trigger regaster, except flip-flop younger decades, through the aND-NOT inputs soy dineny with key elements, and inputs the decoding converter, the logic inputs of aND-NO element are connected to outputs tr1iggerov, reset inputs which are connected to the reset output of the control unit, the first output of the coupler of the paired shifted PULSE connector to the gate inputs of the gated comparators, the second output is connected to the trigger start input and to the input of the paired shifter of the younger decade of the code, and the input of the paired shifter of the shifted arcs of shifted matched pulses of the paired offset pulses; code is connected to the control output of the control unit, the input of which is connected to the first output of a separate paired shifted pulse shaper, the second output of which th connected to strobe inputs gated comparators younger decade code, and an input coupled to the output of the paired shifted. and the pulses of the penultimate junior decade of the code. Sources of information taken into account during the examination 1. USSR author's certificate No. 226975, cl. N OZ K 13/115, 1967. 2. E. Gitns. Information Converters for Electronic Digital Computing Devices, M., Energii / 1975, p. 316-320, fig. 7-11 b, c (prototype). t  , 4 4- “s“ .4I - ““ - / f., N / I i I, u g - USA I I P T 1l “™, J ™ Ij 1 W. ™ -W« ™ Jj