SU567221A1 - Dynamic-memory switching device - Google Patents

Description

one

The invention relates to switching technology and can be used in the construction of switching fields with spatial division of channels in various information systems, such as PBX. Switching devices known to be built on electronic elements and used in automatic telephone installations are known.

Of the known electronic switching devices, the closest in technical essence to the invention is a device containing a matrix consisting of horizontal and vertical women with switching elements at the intersection points of these buses, and successive registers - shift 1.

However, this device has a low speed associated with the complexity of control, which means that in order to switch one of the matrix elements, it is necessary to remove the entire contents of the registers from the device, to process this information in a separate device and write it back to the registers.

The purpose of the invention is to increase the speed of the device.

This is achieved by introducing the first decoder, recording blocks, and gates into the dynamic memory switching device.

reset, address valves, record fans, prohibition element, collective scheme and second decoder. The outputs of the second decoder are connected to the first control inputs of the switching elements, and their inputs are connected to the serial shift registers, the control inputs of which are combined, and the outputs are connected to the first inputs of the corresponding recording blocks, to the second inputs of which the corresponding address gates are connected. inputs connected to the input of the prohibition element and from the output of the collective circuit. we, to the inputs of which the outputs of the recording gates are connected, the inputs of which are connected to the second the control inputs of the switching elements and the control inputs with the corresponding outputs of the first decoder. At the same time, the control inputs of the address valves are connected to the corresponding inputs of the prohibition element, the output of which is connected to the control inputs of the reset valves, and the outputs of the recording blocks are connected to the inputs of the second decipher.

The structural-electrical circuit of the proposed device is shown in the drawing.

A dynamic memory switching device contains a matrix 1 consisting of horizontal and vertical buses with switching elements 2-17 at the intersection points of these buses, and successive shift registers 18, 19, 20. In addition, the first decoder 21 is inserted into the device 30, blocks records 22, 23, 24, relief valves 25, 26, 27, address valves 28, 29, 30, recording valves 31-34, prohibition element 35, collecting circuit 36, second decoder 37. The outputs of the decoder 37 are connected to the first control inputs switching elements 2-17, and its inputs through the relief valves 25, 26, 27 connected to the serial shift registers 18, 19, 20, the control inputs of which are combined, and the outputs are connected to the first inputs of write blocks 22, 23, 24, to the second inputs of which are connected the outputs of address gates 28, 29, 30, inputs connected to the input the prohibition element 35 and with the output of the collecting circuit 36. The inputs of the circuit 36 are connected to the outputs of the write gates 31 - 34, the inputs of which are connected to the second control inputs of the switching elements 2-17, and the control inputs to the corresponding outputs of the decoder 21. The control inputs address valves 28, 2 9, 30 are connected to the corresponding inputs of the prohibition element 35, the output of which is connected to the control inputs of the relief valves 25, 26, 27, the outputs of the writing blocks 22, 23, 24 to the inputs of the decoder 37.

The device works in the following way.

A code is supplied to the inputs of the decoder 21 and the address gates 28, 29, 30.

The code on the inputs of the decoder 21 determines the horizontal number. This code is decrypted in the decoder 21, after which one of the outputs of the decoder 21 appears "1", which is fed to the input of the write valve 34 connected by a second input to one of the vertical busses of the matrix 1. On this bus, clock pulses are sent to the switching elements 14-17. Thus, at the output of the recording valve 34, at each step 4, "1 appears, until the code of the horizontal number is present at the inputs of the decoder 21. This “I in each cycle 4 from the output of the collecting circuit 36 passes to the inputs of the valves 28, 29, 30 and element 35 and thereby opens them only in the cycle 4. To the inputs of the address valves 28, 29, 30 of the device receives the binary code of the vertical number { except code III). This binary code from the outputs of address gates 28, 29, 30 in measure 4 falls on the input of writing blocks 22, 23, 24 and from the output to decoder 37. At one of the outputs of decoder 37 in cycle 4 appears "1. Thus, the control inputs of the switching element in measure 4 receive two ' 1. The first "1 is fed from one of the horizontal buses of the matrix 1, and the second" 1 from the output of the decoder 37 enters the switching elements. At the same time, in the same cycle from the output of the write blocks 22, 23, 24, the binary code of the vertical number is written through the reset valves 25, 26, 27 into the shift registers 18, 19, 20. At the second gate inputs

reset 25, 26, 27 all the time there is "1, since the prohibition element 35 is in the closed state, because at the inputs of the address gates 28, 29, 30 in the initial state of 5 research institutes there are all" O, and in the first mode - binary a code in which at least there is one "O (code III is excluded). After removing the binary code from the inputs of the decoder 21 1I address gates 2-8, 29, 30, the binary code of the vertical number is recorded in the shift registers 18, 19, 20 and the capacitance in the switching element 17 is recharged in each cycle and held in open state. The second mode of operation is for

5 the destruction of the connection between a given input and output. In this case, the binary code of the vertical number is supplied to the inputs of the decoder 21, and the inputs of the address gates 28, 29, 30, code III. This code arrives at the prohibition element 35, which in cycle 4 opens and on its inverse output appears "O, which prohibits the rewriting of the binary code from the output of the recording blocks 22, 23, 24 to the input of the shift registers 18, 19, 20. In the following The cycle 4 at the outputs of the decoder 37 turns out to be “O and the switching element opens the specified input and output.

Thus, in the proposed device, as compared with the prototype, the speed is increased, the required memory volume is reduced, and its control is as close as possible to the control of reed connectors that are currently used to construct switching fields.

Claims (1)

Invention Formula A dynamic memory switching device containing a matrix consisting of horizontal and vertical buses with switching elements at the intersection points These buses, and successive shift registers, characterized in that, in order to increase speed, the first descrambler, write blocks, reset valves, address gates, write gates, element are introduced the prohibition, the collective circuit and the second decoder, the outputs of which are connected to the first control inputs of the switching elements, and the inputs of the second decoder are connected via the corresponding reset valves to successive shift registers, the control inputs of which are combined, and the outputs are connected to the first inputs of the respective blocks, the records, to the second inputs of which the outputs of the corresponding address valves, the inputs of which are connected to the output of the prohibition element and to the output of the collecting circuit, whose inputs are connected to the outputs of the recording gates, whose inputs are connected to the second control the inputs of the switching elements, and the control inputs with the corresponding outputs of the first decoder, while the control is ush; . Sources of information taken into account in the examination 1. UK patent number 1287374, cl. H 4K, pub. 02.02.72.