SU1439680A1 - Dynamic solid-state storage - Google Patents

Abstract

The invention relates to a computing technique and can be used as an operational tool. The aim of the invention is to improve the speed of the device, ic trio contains the J address register, multiplexer 3, regeneration trigger 4, regeneration address counter 5, local control unit 6, clock decoder 7, memory block 8, synchronization unit 11, reverse the counter 12, the decoder 13 of the regeneration time, the generator 14 of the regeneration signals. The device provides aciiHxpoHHbrii regeneration mode, and priority is given to the recording mode or reading if the regeneration time to other addresses is critical, which improves the performance of the device due to the optimal distribution of the device operation time between the pereaepaiqiH and write access. read reading 2 Il. &

Description

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This invention relates to a computational TGXHirKB and can be used as a RAM.

The purpose of the invention is to increase the speed of the device.

Pa Fig, 1 shows a functional diagram of the proposed device; figure 2 is a functional diagram of the synchronization unit.

The device contains (Fig. 1) address register 1, address inputs 2, multiplexer 3, regeneration trigger D, regeneration address counter 5, local control unit 6, clock decoder 7, memory block 8, information inputs 9 and outputs 10, synchronization block J, reverser-counter 12, decryptor 13 at the time when counter 5 contains the next regeneration address, counter 12 contains the number n (n is an integer) of regeneration cycles the regeneration period, minus the number m (m of calls to the block time, i.e., the number of 12 is equal, because the summing input of the counter 12 receives a regeneration enable signal, and the subtracting input receives a regeneration enablement signal, the J4 signal generator — 20 „of access to the 8 — corresponding JLOB regeneration, entry 15 initial

but from the second and the first outputs of block 11. If the incoming 1 is some address 1 for a call, it is set on register 1, from B (of which inputs to the decoder 7 control potentials are supplied to read or write information. At the same time of block 11, KOTOpbifi sets the trigger 22 to a single C (. Standing. Moreover, if the contents of counter 2 are not critical, then a low potential appears at the output of the decoder J3, which 1 hits the HE element 17 and hectares one ms. of the inputs of the element And 18, due to which the output Noise signal from generator JA, pass element 20 of delay; - MI, does not pass through element AND S8 and r element AND JO, closed by a signal from trigger output 22, and then through element MLI 25 - to the second output of block 11, i.e. The regeneration mode turns out to be forbidden. Therefore, the second signal from the output of the element: delay 20 arrives at the second input of the element I 23 and passes through the first output of the block 1J to the block 6 and to the input of the counter 12. decreasing the number of its outputs. The same signal passes to the ENTRY of the trigger 22 through the OR element 24, resetting the trigger 22 to the zero state. The delay element 20 prevents transients when changing modes when asynchronous signal appears. circulation The next signal from the iA generator, if there is no circulation signal at input 6, postunay / chert I 19 and then through the element

installation and entrance J6 appeal.

The synchronization unit 11 contains (FIG. 2) the element NOT 17, the elements 18 and J9, the delay element 20, the element linii 2-1, the trigger 22, the element 23 and elements OR 24 and 25.

The memory unit 3 may be constructed of memory storage elements, for example, of the type K565 RU I.

The local control unit 6 can be performed, for example, an analogue of the serially available control module M-2K U3.0J CLS.

The device works as follows.

The device operates in three modes: write, read and regenerate.

Any access to the accumulator row of block 8 causes regeneration in all storage elements connected to the column read amplifiers (not shown) of Section 8 when the row is inserted. In addition, during the regeneration period, regeneration cycles must be performed to prevent distortion or loss of information. The proposed device allows you to organize an asynchronous regeneration mode, giving priority to the recording mode or sending a scan if the regeneration Burden time at other addresses is not. is critical, Within the requirements of reliable information storage.

Before starting work 1, input signal J5 (Fig. 1) receives an initial setup signal, as a result of which trigger 22 (Fig 2) is set to O,

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Block 6 generates signals on a B1 pz1 chip, recording mode or reading modes, gating the decoder 7, and setting it in O trigger 4,

In the case when the next regeneration address is on the counter 5, the counter n is the number n (n is an integer) of regeneration cycles carried out during the time from the beginning of the current regeneration period, minus the number m (m) i.e., the number of the chip 12 is equal, since the regeneration resolution signal is sent to the summing input of the counter 12, and the whole integer number is sent to the subtracting input) during this output.

0 „„ referring to block 8 corresponding

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but from the second and the first outputs of block 11. If the incoming 1 is some address 1 for a call, it is set on register 1, from B (of which inputs to the decoder 7 control potentials are supplied to read or write information. At the same time of block 11, KOTOpbifi sets the trigger 22 to a single C (. Standing. At the same time, if the contents of counter 2 are not critical, then a low potential appears at the output of the decoder J3, which 1 hits the HE element 17 and ha one ms. of the inputs of the element And 18, due to what the output Noise signal from generator JA, pass element 20 of delay; - MI, does not pass through element AND S8 and r element AND JO, closed by a signal from trigger output 22, and then through element MLI 25 - to the second output of block 11, i.e. The regeneration mode turns out to be forbidden. Therefore, the second signal from the output of the element: delay 20 arrives at the second input of the element I 23 and passes through the first output of the block 1J to the block 6 and to the input of the counter 12. decreasing the number of its outputs. The same signal passes to the ENTRY of the trigger 22 through the OR element 24, resetting the trigger 22 to the zero state. The delay element 20 prevents transients when changing modes when asynchronous signal appears. circulation The next signal from the iA generator, if there is no circulation signal at input 6, postunay / chert I 19 and then through the element

or ; 5 - pa iiTopoii BbixcvJ. block 1.1, res Ilia and rege paradise 1G.

In the event that there is a conversion call at input 16 and the trigger 22 is in a single state, but the regeneration time has reached a critical value, then at the output of the decoder 3 there is a high potential that prohibits G1roho) {sd1; And 23 and allows the regeneration signal to pass through the element And 18, In the absence of the inversion signal and the critical time of regeneration is absent, the control signal pa the regeneration resolution passes through the elements AND 19 and OR 25.

Thus, in the device, priority is given to the write or read access mode, if the regeneration time is not critical, which makes it possible to increase the speed of the device beyond the optimal allocation of its operation time by these modes,

Claims (1)

Invention Formula A dynamic semiconductor memory device containing a memory block, an address register, a multiplexer, a regeneration trigger, a regeneration address counter, a gey.rg generation generator, a clock decoder, and a local control block, the first output of which is connected to the gate input of the clock signals The outputs of which are connected to the inputs of the row selection of the memory block, the inputs of the addresses of the rows of which are connected to the outputs of the multiplexer, the information ghody of the first group of which is connected (11 with bit and the outputs of the first group of the address register, the bit outputs of the second group of which are connected to the inputs of the addresses of the columns of the memory block, the input write-reads and a chip select input of which are connected respectively to the second and third outputs of the local control unit, the fourth trick-rf pcirrj IC DK.CHYU IM To PCPLA .STPPKI in i-pHiTPiia regeneration, inerts-Hbiii and direct KOTOJHM outputs on the farm: s; o () correspondingly with the terminal input of the control unit of the multip.pe.xora, with the input of the prohibition of the ob-1-1-1ii n g local control unit and Brat entrance control; 1 ltek multi; -; plexor, and information pionora Q second D) which i: OAKjrro4eHbi to the regular outputs of the regen address of the regency address, and the outputs of the third group of the register of the address are connected to the information; the inputs of the decoder 5 clock signals, enter; the address registers are the device's address inputs, the information inputs and outputs of the memory block are information-input and output ports, and, Q o t h ia yaaaaaa that, with the purpose, over the speed of the device, there is a reversible counter, synchronization unit and a decoder of the regeneration time, the inputs and output of which are connected accordingly. but to the outputs of the reversible counter and to the input I am allowed to regenerate; - the synchronization unit, the first output of which is connected to the trigger input Q local control unit and the subtraction input of the reverse of the upcoming counter, the summing input of which is no.n; KjD04eH to the second output of the synchronization unit,; the input of the start of regeneration of the local control unit, the installation input to j of the regeneration trigger, and the counting input of the regeneration address counter, the reset input of which is the input of the initial installation of the synchronization unit and The Q input of the reset of the address register is combined and is the input of the initial installation of the device. The access input of which is the synchronization block access input, third;: whose output is connected to the reset input of the reversible counter, the output of the regeneration signal generator with the clock input of the synchronization unit, the reset input which is connected to the output Q regeneration address counter overflow. five Phie.