SU552687A2 - Shaper single pulses, synchronized clock frequency - Google Patents

Description

one

The invention relates to a pulse technique, namely to a synchronized pulse shaper. It can be used to match the asynchronous signals from the digital computer to the clock frequency of the peripheral device.

According to the main author. St. No. 514426 is known for a single pulse shaper, synchronized with a clock frequency, containing input and output triggers and three elements AND 1.

The disadvantage of such a former is the distortion of the output pulse shape. Thus, the leading edge of the output pulse appears with a delay of pf 2m (where m is the delay time of propagation of the signal on a single I element), and rear-delayed.

The distortion of the output waveform (increase in duration) reduces the reliability of the device and may lead to a failure in the system where this driver is used.

The purpose of the invention is to increase the reliability of the driver.

This is achieved by the fact that in the proposed driver of single pulses synchronized with a clock frequency containing input and output triggers and three elements AND, the first input of the input trigger is connected to one of the inputs of the first element AND, the other input of which is connected to one of

input trigger outputs, the output of the first element I is connected to the first input of the output trigger, the output of which through the second element I is connected to the second input of the input trigger, the second output of the input trigger through the third element I connected to the second input of the output trigger, the first input of which is connected by the first input The second element And, the output of the third element And is connected to the additional input of the second element I. This allows you to form the rear edge of the output signal, min output delay trigger and delay on it equal to 2m. FIG. Figure 1 shows the structural electrical circuit of the proposed shaper; in fig. 2, ad — time diagrams of the shaper operation.

The shaper is implemented on potential elements and contains a bus 1 of the synchronized signal connected to the first input of the trigger 2 and one of the inputs of the first element 3, the other input of which is connected to one of the inputs of the trigger 2, the third to the bus 4 clock frequency, and the output to the first input of the output trigger 5 and the input of the second element I b, the other input of which is connected to the output of the output trigger 5, the output to the output bus 7 and the second input of the trigger input, and the additional input to the second input

trigger 5 and with the output of the third element And 8, the first input of which is connected to the second output of the input trigger 2, and the second - with the bus 4 clock frequency.

Timing diagrams show the work of the driver in positive logic.

With a high signal level on bus 1 (Fig. 2, a), triggers 2 and 5 are reset by signals from bus 4 (Fig. 2, b) of the clock frequency through elements 6 and 8.

A low signal level on bus 1 triggers trigger 2 (FIG. 2, c), but prohibits further propagation of the signal from the output of this trigger through element 3 (fig. 2, d). The occurrence of a high signal on bus 1 allows the passage of a pause of the clock frequency through the element 3. Occurring: when the clock frequency is paused, the low level of the signal at the output of the element I 3 triggers trigger 5 (Fig. 2d), but prevents further propagation of the signal the output of this trigger through the element And 6 (Fig. 2, e). The pulse of the clock frequency, having passed through two prepared elements AND 3 and 6, with a delay of 2m appears at the output of the driver. This signal zeroes the trigger 2, forbidding the impulse of the clock frequency pulse through the element I 3 and resolving it, through the element 8 and (8, g). The change in the state of trigger 2 at this moment has no effect on the output signal, since elements 3 and 8 are blocked by a clock pulse. At the end of the clock pulse, after 2m (the time it takes for the signal to pass through the prepared elements 8 and 6), the trailing edge of the output signal is formed at the output of the driver. The resultant low level of the signal at the output of the AND 8 element embraces the trigger 5, which brings the shaper to its initial state.

Thus, when the signal on bus 1 changes from low to high, a single pulse arises at the output of the driver synchronously with the first whole pulse of the clock frequency, and the pulse shape is not distorted.

Such a technical solution makes it possible to improve the shape of the output signal of the known device and thereby increase the reliability of the driver.

Claims (1)

1. Auth. St. USSR № 514426, cl. H OZK 5/13, 13.03.7: 6.