SU1737411A1 - Device for programmed control - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used in process control systems for controlling cyclic processes with sequential excitation of the outputs of the execution unit. In general, a device is a functionally complete module for designing scalable distributed programmable controllers. The purpose of the invention is to expand the field of application by providing arbitrary control of electroautomatics with high precision

Description

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FIGURE #G

intervals. The device contains 1 pulse generator, 2 frequency divider, time counter 3, execution unit 4, program set block 5, first 6 and second pulse synchronizers 7, program memory block 8, address counter 9, command decoder 10, element 11, element NOT 12, first 13 and second 14 elements OR. The frequency of the generator 1 is fed to the input of the divider 2 frequency, which divides it into three frequencies: fi, h. f3, and the frequencies fi and h are fed to the inputs of synchronizers 6 and 7, and the frequency fa through the element IL AND 13 enters the subtractive input of the counter 3 times, s

The invention relates to automation and computer technology and can be used in computer numerical control systems for process equipment for controlling cyclic processes with sequential excitation of the outputs of an execution unit. In general, a device is a functionally complete module for designing scalable distributed programmable controllers.

A device for software control is known, consisting of a carriage position sensor unit, a logic unit, an indication unit, a command generation unit, a power unit.

The disadvantages of this device are its complexity and low reliability due to the large number of sensors installed on the machine.

It is also known a device for software control of cyclic processes, comprising a master oscillator, a frequency divider, a time interval shaping unit, a program dialing unit and actuators.

A disadvantage of this device is its limited functionality, since it cannot control cyclic processes with several time mismatched intervals.

The closest in technical essence to the proposed device is a device for programmed control of cyclic processes, comprising in series a pulse generator, a frequency divider, a program set block and an execution unit.

The disadvantage of such a device is the low accuracy of its operation.

the output of which a pulse arrives at counter 9, a new address is set in it, a command appears at the output of block 8. The decoder 10 command decrypts its number and includes the corresponding executive authority in block 4. The frequency pulses f are received through the element OR 14 to the input of the counter 3 until then. until it overflows. At the same time, its output signal will go to the input of the counter 9 of the address and a new command will be selected with a new operating time, after which the cycle repeats. 5 ill., 2 tab.

The purpose of the invention is to expand the field of application by providing arbitrary control of electroautomatics with a high accuracy of setting time intervals.

This goal is achieved by the fact that in a device for programmed control, comprising a pulse generator, a frequency divider, a time counter, a dialing unit

programs and executive unit, the first and second pulse synchronizers, program memory block, address counter, command decoder, AND element, NOT element, first and second elements are entered

OR, the output of the pulse generator is connected to the first input of the element I, the output of which is connected to the information input of the frequency divider, the first and second outputs of which are connected to the first

the inputs of the first and second pulse synchronizer, respectively, and the third output is connected to the first input of the first OR element, the second input of which is connected to the output of the second synchronizer

pulses, and the output of the first element OR is to the subtractive input of a time counter, the code inputs of which are connected to the first group of outputs of the program memory block, and the time counter recording input

connected to the output of the first pulse synchronizer, the output of the time counter is connected to the control inputs of the first and second pulse synchronizers and to the summing input of the address counter, the input inputs of which are connected to the first output of the program set block, the outputs of the address counter and the group-setting outputs of the program set block - respectively to the groups of address and information inputs of the program memory block, the second group of outputs of which

connected to the inputs of the command decoder, the group of outputs of which is connected to the group of inputs of the execution unit, the output of the last bit to the first input of the second OR element, whose output through the element is NOT connected to the second input of the element I. outputs Writing the address of the code word and Recording the code word of the program set block is connected respectively to the inputs of the record of the address counter and 50 program memory block, the second input of the second element OR is connected to the input of the task of presetting the program set block, which It is also connected to the preset inputs of the time counter, the first and second pulse synchronizers, the address counter, the Dial, Start and Preset inputs of the program set block and the input of the pulse generator are the same-name inputs of the device.

FIG. 1 shows a block diagram of the device; in fig. 2 - time diagram of his work; in fig. 3 - block diagram of synchronization of 6 (7) pulses; in fig. 4 - 5 structured frequency divider circuit; in fig. 5 is a block diagram of the program set block 5.

As can be seen from FIG. 1. The device contains a pulse generator 1, a divider 2 hours-10 tons, a time counter 3, an execution unit 4, a program set block 5, a first 6 and a second 7 pulse synchronizers, a program memory block 8, an address counter 9, a decoder 10 commands, Element AND 11, Element 15 NOT 12, first 13 and second 14 elements OR.

As can be seen from FIG. 3, the synchronizer 6 (7) consists of a D-flip-flop and an element 16. The impulse B of the frequency fa from the overflow output 20 of the counter 3 sets the output of the trigger 15 to the state of a logical unit, opening the element 16. The impulse A of the frequency fi passes through the element AND 16 to its output B and then to the input of parallel loading of the counter-25. On the falling edge of pulse A, the trigger 15 is set to the logical zero state and closes the AND 16 element until the next pulse B.

The time counter 3 is built on synchronous 30 binary binary counters of the type K531IE17, the overflow signal of which is set when the counters reach a state equal to zero. This signal is gated by the input pulse of the frequency fa, and the strobed overflow signal is strictly synchronized with the frequency fa to the blocks 6–9.

As can be seen from FIG. 4, the frequency divider 2 with self-healing consists of triggers 17-19; decoder 20; elements and 40

21-23; elements OR 24, 26 and element NOT 25.

As can be seen from FIG. 5, block 5 of the program set consists of the register 27 of the address of the module, the decoder 28 of the address, the elements of AND 29-31, the counter of 32 cycles, the register 33 of the selection of the operating mode; the decoder 34 of the contents of the loop counter, elements OR 35, 37. elements 2-2И-2 OR 36. 38, trigger 39.

The program set unit 5, depending on the application of the device, may or may not have the means for repeating the cycle a countable (uncountable) number of times.

The device works as follows.

Before starting the program control cyclic (relay) automation using block 5 of the program set zano-. sets in memory block 8: the address of each command is entered into address counter 9, and the contents of the command in memory block 8. The format of the command (code word) consists of the number of the output being excited, the operation bit and the time delay code. The code word is entered through the external connector of the unit 5 (conventionally marked Set in Fig. 1) from an external programming device.

The preset signal of the PU resets the 2 frequency divider to zero, counters 3 and 9, pulse synchronizers 6, 7. In addition, it passed through the OR 14 element, the PU signal keeps the AND 11 element closed. In the counter, zero and in the zero cell of block 8 the memory in the bits of the command number contains a code of zeros, therefore, at the output of the decoder of 10 commands there are no excited outputs. Executive unit 4 is turned off. By the signal of the PU, the triggers of the synchronizers 6 and 7 are set to zero.

When you press the Start button on the remote control unit 5 of the program set, the potential of the preset PU disappears at its output. as a result, the prohibition on the input of element I11 disappears. The frequency of the generator 1 is fed to the input of the splitter 2 frequency, which divides it into three frequencies: f 1, h, fa (see Fig. 2), and the frequencies f 1 and fa are fed to the inputs of synchronizers 6 and 7, and the frequency fa through the element IL I13 enters the subtracting input of the counter 3 times. The frequencies fi, f2, fa are the same and equal to f / W and shifted relative to each other by 120 °.

Since the time counter 3 is in the zero state, when the output of the OR 13 impulse frequency fa at the output of the overflow of counter 3 arrives, a pulse arrives at the input of the counter 9 of the address and the synchronizer inputs 6.7.

In counter 8, a new address is set, a command appears at the output of memory block 8.

The accuracy of setting the command time is determined by the value of At 1: f / 3 G / f, and the exposure range TMmax. - the value of Dg -N, where N is the period of the counter 3.

The output impulse from synchronizer 6 rewrites from the memory block 8 into the counter 3 the time of command operation, and the output impulse from the output of the synchronizer 7 through the element OR 13 subtracts one from the contents of counter 3, the decoder 10 command decodes its number and includes the corresponding executive in block 4 .

Pulses of frequency f are fed through the element OR 14 to the input of counter 3 until it overflows. At the same time, its output signal will go to the counter input.

9address and a new command is selected with a new action time, after which the cycle is repeated.

When the End of Program command appears in the memory cell 8 of the memory, it will go from the output of the decoder 10 through the element OR 14 to the input of the element NOT 12, and its output signal will close the element And 11, the processing of the program is completed.

The work cycle is clearly visible in FIG. 2. The accuracy of setting the time is determined by the frequency of the generator and can be obtained any.

Divider 2 frequency (Fig. 4) works as follows.

If the PU signal is excited, the operation of the decoder 20 is prohibited, and the outputs of the flip-flops 17, 18, 19 are set to zero by the asynchronous reset inputs and close the output of the frequencies fj, f2, Tz through elements 21.21, 23. As soon as the PU signal disappears, the decoder 20 is allowed to work, the information inputs of which are supplied with a three-bit status code of the trigger 17,18, 19. The output signals of the decoder 20 together with the OR elements 24, 26 and HE 25 provide synchronous in normal mode and asynchronous in case of failure the change in the state of the trigger 17, 18.19.

The table of transitions and states of triggers 17,18,19 looks as follows (see Table 1).

The symbol f denotes a synchronous transition; the change of states of the trigger 17,18,19 occurs on the trailing edge of the frequency f pulse. The x symbol denotes asynchronous transition when divider 2 fails,

The failure states of the triggers 17,18.19, as well as the initial state O, at the time of arrival of the next frequency clock f, the status of the flip-flops under code 4 (see the table) are generated and the impulse frequency fa is unconditionally outputted on the back edge of the frequency clock f, the state of triggers 17, 18, 19 from state under code 4 (see table) to state under code 1 was changed. Further, during normal operation of divider 2, the status of triggers change in accordance with the code scheme: 4.2, 3.1. In fact, the frequency divider 2 is a shift register with error correction on yourself, the individual bits of the inputs

which (outputs of the flip-flops 17, 18, 19) are controlled alternately by issuing pulses of the frequency fl, T2, f3.

The frequency divider 2 is reset by the PU signal before the start of the cycle. Detection of the signal The end of the program, the generator 1 is blocked (see Fig. 1) and the divider does not work, since the frequency f is terminated at its input. After that, the device can be reprogrammed or the previous program can be resumed by pressing the buttons PU, Start.

Program set block 5 (see FIG. 5) performs the following functions:

-selection of the module in accordance with the address specified from the external programming device;

-transmission of the program from the programming device to the memory module;

- organization of the mode of operation of the module in accordance with the command transmitted from the programming device.

Block 5 of the program set works as follows.

Previously, an external command from the external programming device receives the PU-K command, which zeroes the contents of registers 27, 33, counter 32 and flip-flop 39. The inverse output of the latter is set to state 1 - a PU signal will appear, whose effect on the elements of the program control unit is described above. During the entire programming time of the device (module), its generator 1 (see Fig. Is blocked by the Blok signal and the frequency f from its output is not output.

With the start of programming, the external programming device places in

The codeword bus operand consisting of 3 fields: module address field, module module cycle parameter field (number of cycle repetitions), module mode field — and generates sync signals Module selection (M selection) and Record mode (Sp. ).

But the clock signal. Selecting M from the module address field reads the address code into the register 27. The outputs of the register 27 are connected to the decoder 28, the latter has N + 1 outputs. Such decoders are located on all modules of the controller, however, only one of the decoder outputs is used in each of the modules, and the same outputs cannot be used in different modules. Thus, the selection of some l-oro module occurs. The next moment, the signal comes Zp. The mode that writes the cycle parameters to the counter of 32 cycles from the field, the number of cycle repeats for the selected module and simultaneously writes the mode code to the mode register 33 from the field of operation. The latter consists of 3 bits encoded in accordance with the table. 2

After the l-th module is selected, its mode of operation and the number of cycle repetitions are set, the external programming device sends to the module 8 of the module memory the cycle program, i.e. performs the following actions in the order outlined.

Sets the address of the code word on the bus to the address of the memory block over which the next code word should be written. Delivers the sync signal of writing the address of the code word to the counter 9 of the address of the block 8 of the memory. Addr Cop. Sets a code word on the code word bus. Delivers the sync signal of writing the code word to the memory block 8 at the address located in the address counter 9 Kp. Cop.

This sequence of actions is repeated until all the commands (code words) of the program cycle are recorded in the memory block 8 of the memory. Then, the Blok signal is eliminated, and after this, if all the other modules are already programmed, a Start signal is generated. If one of the module operation modes is set, i.e., one of the outputs of the register 33 of the mode has a high logic level, then by the Start signal, the trigger 39 is set to the zero state on the inverse output, i.e. the PU signal disappears and the program is started. After the last End of Program command is extracted from memory block 8, the signal of the same name will set trigger 39 to unity on the inverse output, i.e. the control signal will appear and the end of program signal will disappear, since zero from memory block 8 The address No command is extracted to the address and the 10 command decoder will switch the unit level from the output End of the program to the unused output (indifferent). The pulse signal generated in this way. End

programs will subtract 32 cycles from the counter. The decoder 34 will set a logical zero at its only output if the contents of counter 32 are zero, or

5 logical unit, if it is not equal to zero.

The 2-2I-2ILI elements are assembled with the conditions when, after the occurrence of a signal from the PU, which establishes the initial position of the module circuit, before starting the program, it is necessary to automatically generate a Start signal in the module itself. This occurs if counter 32 has not yet reset and mode 2 is selected (see

5 tab. 2) or if mode 3 is selected. If mode 4 is selected, the program will not restart, i.e. the program (cycle) is run once.

0 Form and invention

A software control device comprising a pulse generator, a frequency divider, a time counter, a program set block and an execution unit,

5 characterized in that, in order to expand the scope of application by providing arbitrary control of electroautomatics with high precision of setting time intervals, the first and second pulse synchronizers, a program memory, an address counter, a command decoder, an element AND, an element NOT, the first and second elements OR, and the output of the pulse generator

5 is connected to the first input element And, the output of which is connected to the information input of the frequency divider, the first and second outputs of which are connected to the first inputs of the first and second synchronizers

0 pulses, respectively, and the third output is connected to the first input of the first OR element, the second input of which is connected to the output of the second pulse synchronizer, and the output of the first OR element to the subtracter input of a time counter, whose code inputs are connected to the first group of outputs of the program memory block , and the input of the recording of the time counter - to the output of the first pulse synchronizer, the output of the counter

0 time is connected to the control inputs of the first and second pulse synchronizers and to the summing input of the address counter, which defines the inputs of which are connected to the first output of the program set block,

5 outputs of the address counter and a group of programmable outputs of the program set block — respectively to the groups of address and information inputs of the program memory block, the second group of outputs of which is connected to the inputs of the command decoder, group

the outputs of which are connected to the group of inputs of the execution unit of the last bit, with the first input of the second element OR, whose output through the element is NOT connected to the second input of the AND element, outputs Writing the code word address and Writing the code word of the program set block, respectively, to the write inputs of the address counter and the program memory block, the second input of the second element OR

connected to the output of the preset installation of the program set block, which is also connected to the preset inputs of the time counter, the first and second pulse synchronizers, the address counter, the set inputs, the start and the preset settings of the program set block and the input of the pulse generator are the same inputs of the device.

Table 1

table 2

Counter output J

eight

R

l

one

BUT

g

§

g

FIG. 2

Fig.Z

t

and

sixteen

Zp ASp KA

8 Midrange 9 FIG. five

Sn Adr COP

Claims (1)

Claim A device for program control, comprising a pulse generator, a frequency divider, a time counter, a program dialing unit and an executive unit, characterized in that, in order to expand the scope by providing arbitrary control of electroautomatics with high accuracy of setting time intervals, the first and second pulse synchronizers, program memory, address counter, command decoder, element AND, element NOT, first and second elements OR, and the output of the pulse generator is connected to the first input of the AND element, the output of which is connected to the information input of the frequency divider, the first and second outputs of which are connected to the first inputs of the first and second pulse synchronizers, and the third output is connected to the first input of the first OR element, the second input of which is connected to the output of the second pulse synchronizer , and the output of the first element OR to the subtracting input of the time counter, the code inputs of which are connected to the first group of outputs of the program memory block, and the input of the recording of the time counter to the output of the first pulse synchronizer, the output of the time counter is connected to the control inputs of the first and second pulse synchronizers and to the summing input of the address counter, the input of which is connected to the first output of the program set block, the outputs of the address counter and the group of set outputs of the program set block are respectively the address and information inputs of the program memory block, the second group of outputs of which is connected to the inputs of the command decoder, the group is connected to the output of the preset job A set of programs, which is also connected to the inputs of the preset time counter, the first and second pulse synchronizers, the address counter, the inputs Set, Start and Preset of the block of the program set and the input Blocking the pulse generator are the same device inputs. the outputs of which are connected to the group of inputs of the executive unit of the last bit, with the first input of the second OR element, the output of which through the element is NOT connected to the second input of the AND element, outputs 5 Write the address of the code word and Write the code word of the block of the program set respectively connected to the inputs of the record counter address and a program memory block, the second input of the second OR element Table 1 Status code The initial state Clock frequency New condition Status code T4 tk T2 T4 tk T2 0 0 0 0 X 1, 0 0 4 1 0 0 1 f 0 1 0 2 2 0 1 0 t 1 0 0 4 3 0 1 1 X 1 0 0 4 4 1 0 0 0 0 1 1 5 1 0 1 X 1 0 0 4 6 1 1 0 X 1 0 0 4 7 1 1 1 X 1 0 0 4 table 2 Number p / p Register outputs 33 Mode of operation 3 2 1 1 0 0 0 The module should not work 2 0 0 1 • The module must repeat the cycle program K times recorded in memory 8; the number K is in the counter 32 3 0 1 0 The module should stop repeating the cycle only when the Blk signal arrives from the outside 4 1 0 0 The module should execute the cycle once FIG. 3