SU1437833A2 - Program regulator - Google Patents

Abstract

The invention relates to automation and computing technology and is intended for software control of technological processes and is additional to the author. N 1156006. The aim of the invention is to expand the functional possible

Description

go

This is due to the operational layout of the adjustment programs from the standard subroutines. The device contains a block of 1 memory, a register of 2 addresses, a register of 3 times, a divider 4 frequencies, a reversible counter 5, a generator of 6 pulses, a register of 7 tasks, the first element AND 8, the first 9 and the second 10 elements OR, the first 11 and the second 12 delay elements, address storage unit 13, control panel 14, control counter 15, second element 16, third delay element 17, the device realizes the possibility of abruptly changing the contents of the address register (counter) by substituting the address into it

the readable program from the address storage unit, which leads to the organization of an arbitrary order of reading the programs. The change of this sequence of program execution is carried out with the help of an on-line change of the program recorded in the address storage unit as a result of the corresponding control signals being supplied. In this way, it is possible to build control programs from typical subroutines, i.e. it is possible to receive any adjustment programs without changing the sequence of the following elementary adjustment programs in the main memory block. 2 Il.

 t

The invention relates to automation and computing and is intended for software control of technological processes.

The chain of the invention is to extend the functionality by providing an operational layout of the control program from the typical subroutines.

Fig. 1 shows a device for software control; FIG. 2 shows a functional diagram of the control panel.

The device for software control (FIG. 1) contains a memory block 1, an address register 2, a time register i, a frequency divider 4, a reversible counter 5j, an impulse generator 6; bs, a task register 7, the first element AND 8, the first 9 and second 10 elements OR, the first 11 and second 12 delay elements, the address storage unit 13, the control panel 14, the control counter 15, the second AND 16 element, the third delay element 17, memory block outputs 18-21, group E .Hard 22.1 and informational 22.2 outputs of the control panel 14 of the control unit, shock, - 23-25, outputs of the control panel 14 of the control ,,, input 26 for start-up and 27 device stop.

Remote control 14 (Fig.2) co; Holds generator 28, trigger

29 one-shot 30 and 31, a dial-up field 32, which consists of the address set field 32.1 and the information set field 32.2, the push-button switches 33-36.

Memory block 1 is designed to store programs.

The address register 2 is intended to set the address of the programs in block 1 of the type that must be executed at this stage.

Register 3 is intended to count the execution time of a given program.

 The frequency divider 4 is designed yes; l reduces the pulse frequency from the output of the 6 pulse generator in accordance with the information present at its information inputs.

The reversible counter 5 is designed to change the setpoint and generate output signals of the device.

The pulse generator 6 is designed to set the clock frequency of the device.

Register 7 of the task is intended for storing information, which is determined by the Yushi division factor of the 4-frequency divider.

The first element And 8 is designed to generate a signal for the end of the cycle of operation of the device.

five

0

The first element OR 9 is designed to generate a signal to zero the address 2 register when the device starts and goes to the beginning of the work cycle.

The second element, OR 10, is intended to form a control signal when the device is started up and go to the next program.

The first delay element 11 is designed to match the moments at which the read control signal arrives at the V input of memory 1 and the code at its address input.

The second delay element 12 is intended for matching the information occurrences at the outputs of the memory unit 1 and the arrival of control signals to the time and task registers 3 and 7.

The address storage unit 13 is intended to set the addresses of the readable programs when they are read from the memory unit in an arbitrary order.

The control panel 14 is designed to modify the contents of the block 13 of storage of addresses, set the starting address in the control counter 15 and generate a signal that determines the mode of operation of the device.

The control counter 15 is designed to set the address at which information from the address storage unit 13 is read.

The second element AND 16 is intended to form a write signal in the address register 2.

The third delay element 17 is intended to match the information occurrences at the D-inputs of address register 2 (response time of the control counter 15 and the address storage unit 13) and the arrival of a signal at its C input.

The device for software control works as follows.

In the first cycle of operation, the signal 1, which starts the generator of 6 pulses, is fed to the start-up input 26; the first element OR 9 zeroes the 2 address register and passes to the output of the second element OR 10. In the second cycle, a signal is output from the first delay element 11 to managing vkots. memory block 1. This signal from memory block 1 reads the program at the address specified by register 2 addresses. On the third cycle of the device

From the output of the second delay element 12, a signal is sent to the control inputs of the recording of the register 3 times, the registers 7 of the task and from the first 18 output of the block 1 of the memory to the control C-input of the reversible counter 5. By these signals the initial code is entered into the register 3 of the time time from the third output 20 of block 1 of memory, different from zero, and in register 7 of the task - the code determining the division factor of the divider 4 frequency, from the second output 19 of block 1 of memory. When writing information (some setpoint value) to the reversible counter to 5 from the second output 19 of the memory block 1, the control inputs of the register 7 of the task, which determine the counting direction of the reversible counter 5, should have no signals. This is achieved by the fact that at the same time (i.e., in one program) with the entry of a new setpoint value into the reversible counter 5, the specified bits of the register 7 of the task are reset. In order to ensure the normal functioning of the device, resetting the bits of the register 7 of the task that controls the account occurs somewhat earlier (on the leading edge of the signal from the output of the second delay element 12) than changing the setpoint in the reversing counter 5 (on the falling edge of the signal from the first output 18 memory block 1). At the fourth output of the memory block 1, a signal 1 is generated, which is fed to the counting input of the control counter 15, increasing its content by one, and to the input of the third delay element 17.

The following modes of operation are possible.

1. The sequential read mode of programs recorded in memory block 1. In this case, at the output 25 of the control panel 14, a single signal is missing. On its other outputs, the signals can be arbitrary. The second element AND 16 is locked and the signal 1 from the output of the third delay element 17 will not pass to the C input of the address 2 address and change its state. The pulses from the generator output 6 pulses arrive at the counting inputs of the divider 4 frequency register 3 time and the first input of the first element And 8. On the falling front of these pulses the contents of the register

3 times reduced by one. With a complete reset of the register 3 times, a single signal is generated at its overflow output, which, arriving at the counting input of the register 2 address,

increases its content by one,

and through the second element, OR 10 determines the start of work on the new program. If the program is performed, the device works. Before reading

gist 2 addresses on the signal received at the C-input register 2 addresses. This information sets the address, reduced by one, of the cell in memory 1 of the memory where the program is stored, executed in the next step. The transition to the execution of the next program occurs, as in the first mode.

programs from memory block 1, the contents of address register 2 are incremented by one. With each occurrence of the signal at the output 21 of the memory block 1, the contents of the control counter 15 are incremented by one, from the address storage block 1, the new information is read and written to the address register 2. The transition to the new cycle considers a smooth change in the content of the reversible counter 5 for some time, then in this case the task register is written with the code defining the rate of change of the set of the reversible counter 5 and the direction of change. The signals from the output of the 4 frequency divider, arriving at the counting input of the reversible counter 5, depending on the signals at the inputs of the counting direction control, increase or decrease the content of the reversible counter 5.

The execution of the last program contained in memory block 1 is accompanied by an entry into register 3 of the zero code time. B resulting in a signal received at the C-input

register 3 times, its state does not change, single signals will still be present on inverse outputs. The next pulse from the generator output 6 pulses passes to the output of the first element AND 8 and then goes through the first element OR to the zero reset of the address 2 address, and through the second element OR 10 and the first delay element 11 to the control V-input of the memory 1. The entire operation cycle of the device is repeated anew. The device is stopped by sending a signal to the input 27 of the device.

2. Random reading mode of programs from memory block 1.

At the output 25 of the remote control 14, a single signal is present. There are no signals at outputs 23 and 24. If, after executing a program stored in memory block 1 in a cell with a zero address (this program is always executed first in both modes), it is required to execute some specified program, then some initial code is entered into control counter 15. The address determined by this code reads information from the address storage block 13, which is rewritten into address register 2 according to the signal received at the C input of the address register 2. This information sets the address, reduced by one, of the cell in memory 1 of the memory where the program is stored, executed in the next step. The transition to the execution of the next program occurs, as in the first mode.

five

programs from memory block 1, the contents of address register 2 are incremented by one. With each occurrence of the signal at the output 21 of the memory block 1, the contents of the control counter 15 are incremented by one, from the address storage block 13, the new information is read and written to the address register 2. Transition to a new cycle

0

five

Bots and device shutdowns in this mode are accompanied by the processes described above.

The control panel 14 operates as follows.

Using the keypad switches 32, some information is accumulated, which is fed to the output 22 of the console 14. Using the key switches 33 and 34, the trigger 29 is set to either one or zero state, respectively. The state of the trigger 29 determines the mode of operation of the device as a whole. Using the push-button switches 35 and 36, the one-shot 30 and 31 are triggered, and the signals generated by them are fed to the outputs 23 and 24 of the control panel 14.

If necessary, reprogramming of the Q address storage unit 13 and the execution of a new cycle other than the previous one is possible.

In order to reprogram the address storage unit 13, information is collected on the dial fields 32.1 and 32.2 of the control panel 14 (see Fig. 2). According to the signal generated at the output 23 of the console 14, the code dialed at the address outputs 22.1 is recorded in the control counter 15, which sets the cell address of the address storage unit 13, in which the information changes. According to the signal generated at the output 24 of the control panel 14, the new information from the information outputs 20.2 of the control panel 14 is recorded in the address storage unit 13. Next, the next addresses and information are recruited on the type fields, and the entire writing process is repeated. So n.Do5

0

five

7

until the required update of the maintenance of the address storage block 13 is completed.

The occurrence of signal 1 at the fourth output 21 of memory block 1 is determined during programming. This signal may be present in each program. Then, substituting into the register 2 the addresses of the code from the block 13 of storing the addresses, it is possible to execute the programs recorded in the block 1 of the memory in arbitrary order. If signal 1 at the fourth output 21 appears only when certain programs are executed, then a combination of the first and second operating modes is provided. In the sections where the signal at the fourth output 21 is absent, the device will operate as in the first mode (the state of the address 2 register changes with the arrival of pulses at its counting input).

Thus, the device possesses wider functionality due to the provision of the operative formulation of an adjustment program from a set of typical subprograms without increasing the total memory size of the adjustment program. In addition, by increasing the volume of the address storage block, it is possible with the same number of programs as a result of repeated access to them to build longer device operation cycles. This leads to a significant reduction in storage space.

ten

15

20

25

thirty

35

8338

Claims (1)

The invention The device for software control on the author, St. N-1156006, characterized in that, in order to expand the functionality by providing an operative layout of the control program from the type routines, further comprises an address storage unit, a control panel, a control counter, a second And element and a third delay element, and a fourth the output of the memory unit is connected to the counting input of the control counter. and with the third delay element, the output of which is connected to the first input of the second element, the output counter of the control counter is connected to the address entry group of the address storage unit, the output output group of which is connected to the information input address register group, the information output group of the remote control is connected to information inputs the address storage unit, and the group of address outputs of the control panel is connected to the information inputs of the control counter, the first and second control outputs of the control panel The control unit is connected to the control inputs of the control meter and the storage unit. Addresses, respectively, the third output of the control unit is connected to the second inputs of the second element, the output of which is connected to the control input of the address register, while the output of the first element is connected to the third input of the second element. OR.