SU1569804A1 - Program control device - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and computing devices. The aim of the invention is to save the volume of the memory block when managing systems according to a " hard " time cyclogram having different time cycles. The device contains an input counter 1, a decoder 2, an output register 3, a memory block 4, a delay element 5, an address counter 6, input 7 and output 8, M first registers 9 ₁ ... 9 _M shift, N second registers 10 ₁ . ..10 _N shift, first 11 and second 12 multiplexers, additional counter 13, first 14 and second 15 triggers, third multiplexer 16. This device allows to reduce the size of the memory block by eliminating redundant information by converting the "long" commands into " short. " 1 il.

Description

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The invention relates to automation and computing and can be used as a device for real-time system control.

The aim of the invention is to save the device memory by reducing part of the amount of redundant information by equalizing the bit of the time interval code and the operation code in the aggregate of the most repeated commands, while the long commands are broken up into several normal ones.

The drawing shows a block diagram of the proposed device.

The device for software control contains an input counter 1, a decoder 2, an output register 3, a memory block 4, a delay element 5 (a cascade of one-vibrators), an address counter 6, the output of which is connected to the address input of the memory block 4, the first input of the input counter 1 is the device input 7, the output of the delay element 5 is connected to the input of the address counter 6, the output of the output register is connected to the decoder 2, the output of which is the output of the device 8. which contains the first 9-9y and the second 10d-10P groups of shift registers, the first II and second multiplexers 12, an additional pulse counter 13, the first 14 and second 15 flip-flops and a third multiplexer 16. The apparatus operates as follows.

A normal command is a command of a given length, the width of which allows the issuance of the most frequently encountered commands, consisting of operation codes and time intervals between commands.

Each memory location of memory 4 contains an operation code and a time interval code at which the next command should be executed, as well as a sign of following long commands that indicates its first and last address. In order to use the memory block most efficiently, the long commands are divided into several normal commands.

In the initial state, the 6-address counter is set to the zero state, the trigger 14 is in the initial state, the signal from its output sets the multiplexer 11 to the position

0

five

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five

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when the input 7 is connected to the counting input of the counter 13, and the state of the counter 1 can be arbitrary, since the transfer output of the counter 1 is blocked by multiplexer I1. In all bits of input 1 and additional

13 counters recorded units, first

14 and second 15 triggers installed

to the zero state, while the zero state of the counter 6 of the address corresponds to the address of the first cell of the memory block 4, and the input 7 of the device through a swarm multiplexer 11 is connected to the input of the additional counter 13.

The input frequency signal received at input 7 of the device causes the overflow signal of the additional counter 13, which through the input of multiplexer 16, arriving at the control input of memory 4, reads the contents of the first memory cell in m first, registers 9, - 9m the shift and in n bits of the output register 3 according to the signal from the control output of the memory block 4. From the output of the additional counter 13, the signal also enters the input of the trigger 14, which remains in the initial state in the case of passing the usual command. The code of the time interval recorded in the m first registers 9 ″ - и and the shift, through which the next command must be executed, arrives at the inputs to the additional counter 13. The signal delayed by the delay element 5 increases the content of the counter 6 of the address by one. The operation code from the n bits of the output register 3 is fed to the input of the decoder 2 and the control signal appears at the output of the device. The input frequency signals through multiplexer 11 count the time interval between the commands, and the overflow signal of the additional counter 13 causes the contents of the second memory cell of the memory 4 to be read, etc. Further, the operation of the device is repeated when ordinary commands are received.

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The reading of long instructions from memory block 4 is carried out sequentially in the form of 1 constituent parts of a command, which differ from ordinary commands by a sign of identification.

The device, when executing a long command consisting of several ordinary commands, operates as follows.

Let the next overflow signal of the counter 13, which is fed through the multiplexer 16 to the control input of the block 4, the memory, reads the contents of the memory cell that has the recognition of a long command. At the same time, the signal from the control output of the memory 4 with the arrival of the input frequency (input 7) triggers the trigger 15, the output of which brings the multiplexer 16 to the state that turns off the output of the counter 13 and connects the input frequency to the delay element 5 and controls input block 4 memory. Upon triggering trigger 14 through multiplexer 12, the transfer output of input counter 1 is connected to the input of additional counter 13. Simultaneously, the signal from the second output of multiplexer 12 reads information from the second n outputs of memory block 4 in n shift registers 10 - lOn, which are written to the output register 3 is prohibited by the signal from the output of the multiplexer 12. In this case, the code of the time interval of the address of the long command is recorded in the n first 9D – 9t shift registers according to the signal from the second output of delay element 5, and the operation code is in the second group of registers 10 4 - 10P. Further, with the arrival of input frequency pulses through multiplexer 16 with a delay, the content of address 6 is incremented by one and sequential reading of inLormation from memory block 4 with a corresponding shift of previously recorded inLormation in n of the first corporal of registers 9 – Hdnig and n of the second group of registers 10ts - 1 Op shift, respectively, before the arrival of a signal with a sign of the last address of a long command. With the drive of the 1st (last) address, the control output of the memory block 4 receives the trigger 14, and the trigger 15 pushes the input frequency back to its original state, connecting the output of the additional counter 13 via the multiplexer 16 to the control input of the block 4 memories and to the input of the delay element 5.

At the same time, the signal from the output of the delay element 5 through the multiplexer 12 records the time code of the first and second groups of outputs m of the first registers 9–9 tons of the motor to an additional 13 and input

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I counters, and the code of operations from the outputs n of the second registers 10 - 10 „shift to the output register 3 and through the decoder, rator 2 to the output 8 of the device.

The time interval is counted by the input frequency signals, the overflow signal 4 from the additional counter 13 causes the reading of the contents

The next regular cell of memory block A and further the operation of the device is repeated.

The initial recording in the memory block 4 can be carried out by either the additional address input and the input of recording pulses (the - - initial recording circuit is not shown).

In the proposed device, the memory capacity is reduced due to the exclusion

20 fields of memory containing the address of the next command, which consequently reduces hardware costs. In addition, the device for software control compared to the known

25 makes it possible to reduce the size of the memory block by eliminating redundant information by converting command lengths into short ones.

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Claims (1)

Formula invented g five A software device comprising an input counter, a decoder, an output register, a memory unit, a delay element, and an address counter whose output is connected to the address input of the memory unit, the first input of the input counter is the device input, the first output of the delay element is connected to the counter input, the Q address, the output register output is connected to the decoder, the output of which is the output of the device, characterized in that, in order to save memory space when operating the systems according to a hard time cyclogram, and different cycles, first and second rp / r / are entered into it: i shift registers, first second and third multiplexers, additional Q pulse counter, first and second triggers, while the first group of outputs of the memory block is connected to the serial inputs of the shift registers the first group, the second group of outputs of the memory block is connected to the inputs of the sequential recording of the shift registers of the second group, as well as the first group of inputs of the output register, respectively, the group five the first outputs of the shift registers of the first group is connected to the first group of information inputs of the additional pulse counter; the group of second outputs of the shift register of the first group is connected to the group of information the inputs of the input counter, the transfer output of which is connected to the first information input of the first multiplexer, the control input of which is connected to the forward output of the first trigger, and the output to the counting input of an additional pulse counter, the installation input of which is connected to the input input of the counter, with the input records of the output register and with the first output of the second multiplexer, the second output of which is connected to the second group of inputs of the shift registers of the second group, whose outputs are connected to the second group in of the output register moves, in / out the output of the delay element is connected to five five a group of second bit inputs of the shift registers of the first group and with the information input of the second multiplexer, the information input of the device is connected to the second information input of the first multiplexer and the clock input of the second trigger, whose information input is connected to the control input of the second multiplexer, with the output of the control information the memory unit and the information input of the first trigger, the control input of which is connected to the overflow output of the additional pulse counter and to the control input of the third multiplexer having a first information input coupled to an output of the second flip-flop, a second data input of the third multiplexer is connected to an information input device and an output tre tego multiplexer connected to the input of delay element and to the input of the read block memory.