SU1439533A2 - Program control device - Google Patents

Abstract

The invention relates to automation and computing and can be used as a device for controlling systems in real time. The purpose of the invention is to enhance the functionality by introducing an idle mode. The device contains an input counter 1, a decoder 2, an output register 3, a memory block 4, a delay element 5, an address counter 6, a D-flip-flop 7 and an AND 8 element. Each cell of the memory block 4 contains an operation code, a time interval code and a bit mode selection. In the device, by introducing a standby mode, it becomes possible to organize feedbacks: from the controlled system, a ready signal. The device allows control of a system requiring a wide range of time intervals between commands: from microseconds to hours. No additional hardware costs are required. 2 Il. | se cd & 0 od k)

Description

This invention relates to automation. ke and computer technology and can: find application as a device; you can: 1, etched systems in real time. I The purpose of the invention is the expansion of functional capabilities by combining the expectation mode. Figure 1 shows the structural device heme; figure 2 - time and a diagram of his work.

The device contains an input counter 1, a decoder 2, the output register

3, memory block 4, item. 5 delays, adgreader counter b, trigger B, element 7, element 8,. Each cell of memory block 4 contains the operation code, time interval code, and mode select bit. The initial recording in block 4 of memory can be disconnected by different methods (pickup methods (chain of beginnings: common | zaic; si of memory block, initial setting of input counter 1 and counting. Address b are not shown in the diagram), sd The device works like a dog and - in a manner.

 It is the command in which it is installed. | Mode selection bit (logical 1 in; | additional discharge of block 4 of memory TH) S device goes into wait mode, t, e, the next command is executed after arrival of the signal x from the second to the second input of the device controlled systeg-ea. : in the initial state of the VO, all the rows of the input counter 1 are recorded: single, D- trigger 7 and counter b ipeca obkulesh, which corresponds to the address of the first cell of memory 4. Signal input frequency by enrolling ™ shit on. The first input of the device, which calls up the overflow signal of input counter 1, which, having entered the control input (readout) of memory block 4, reads the contents of the first cell into the output register 3. Operation code from the high-end output bits. register 3 is fed to the input of the decoder 2, and control signals appear at the output of the device. From the release of the lower bits of register 3, the code of the time interval through which the following code must be executed

The cue is recorded in the input counter 1. From the output of the register mode selection bit 3, the signal is sent to the D input of the trigger 7, which is sent to the signal center.

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the overflow of counter 1 is set to the state (zero or one) determined by the signal at its D input. If the mode select bit is not set, the D-flip-flop 7 is set to the zero state and allows passing the overflow signal of the counter 1 delayed by the element 5 by the element 8. This signal increases the contents of the counter 6 of the address by one.

The input frequency signals count the specified time interval to the melody with commands. The overflow signal of counter 1 causes the contents of the second cell of memory 4 to be read, and so on. until in the next command the mode selection bit is set. In this case, the D-flip-flop 7 is set to one and prohibits the overflow signal to pass through the AND 8 element, so the address code in the counter b does not change the address code. The device goes into standby mode. The overflow signals in memory block 4 read the contents of the same memory cell, whose address is stored in the address counter B. In the command for which the device goes into standby mode, it is advisable to set a time interval code of this size, units are written to all bits of the input counter 1, then an overflow signal will occur on the first pulse of the input frequency signal, thereby reducing the dead time devices. By the ready signal from the controlled device, which enters the R input of the D flip-flop 7, the latter switches to the zero state and allows the overflow signal to pass through the And 8 element. The contents of the address bar b are incremented. The arrival of the next overflow signal will cause the contents of the memory cell, etc., to be mixed together. In the future, the device will repeat. Chips from the K155 series can be selected as the device element base.

In the device, by introducing an idle mode, it becomes possible to organize feedbacks; from the controlled system, the ready signal, in which the connection is simple and does not require the introduction of idle commands. In addition, to form long

time intervals between teams can use external timers. The device allows control of a system requiring a wide range of time intervals between commands: from microseconds to hours. No additional hardware costs are required.

Claims (1)

Invention Formula Device for software control aut. St. No. 1252759, characterized in that, in order to expand functional possibilities. Owing to the introduction of the standby mode, a D-trigger, an AND element, an extra bit into the memory block and an extra bit into the output register are entered into it, with this C-input of the D-flip-flop connected to the output of the input counter, D-input - To the output of the additional bit of the output register, the R-input is the second input of the device, the inverse output of the D-flip-flop is connected to the first input of the AND element, the second input of which is connected to the output of the delay element, and the output element AND is connected to the input of the address counter. Vmdnoi sieyusl pl P PP