SU1156006A1 - Device for programmed control - Google Patents

Abstract

SOFTWARE CONTROL DEVICE5 contains a memory block whose address inputs are connected to the outputs of the address register, the first and second outputs are connected to the control and informational inputs of the reversing counter, respectively, and the third outputs are connected to the information inputs of the time register, the counting input connected to the output of the pulse generator and the counting input of the frequency divider, the stop and start inputs of the device are connected to the corresponding inputs of the pulse generator, and the outputs of the reversible counter are the outputs and devices, characterized in that, in order to increase the speed of the device, the task register, the AND element, the first OR element and the second OR element and the first and second delay elements connected in series are entered into it, the output of the first delay element is connected to the control input the memory unit, and the output of the second delay element - with the control input of the register of the task, the information inputs of which are connected to the second outputs of the memory unit; the first outputs - to the information inputs of the frequency divider, and the second outputs - to the input By controlling the direction of counting the reversible counter, S is the counting input of the frequency divider connected to the output, the first and second inputs of the AND element are connected to the inverse outputs of the time register and the output of the pulse generator, respectively, and the output is connected to the first input of the first OR element whose output is connected to reset the address register, and the second input is with the device start input and with (35 the first input of the second OR element, the second input connected to the output of the time register and the DG5 counting input register and addresses.

Description

The invention relates to itomatization and computer technology and is intended for software regulation for 1 st technological processes.

The purpose of the invention is iioBbriueFine device speed.

The drawing shows a diagram of the proposed device,

The device contains block 1 and; -; t register 2 addresses, time register 3 time divider 4 frequencies, reversible slash 5, generator 6 imghuls, task register 7, element if 8, first and second elements of YPI 9 and 10 and the first and second 11 and 12 delay elements

The device works in the following way.

In the first clock cycle, at the device start input, a signal passes through the element OR 10 to the input of element 11 and through the element ITSH 9 to the input of the register 2 reset, which pesyjibatt can be implemented as a free memory - wah, the initial address code 0 is set. .0.

The second cycle at the input of the element 12 and at the control input of the block appears - a signal passes through the element 11 from the output of the ISH 10 element resulting in a sign at the outputs of the information block 1. recorded and the cell with the address set in registers; 2,

In the third cycle, the signal from the output of element 12 is supplied to the control 7 of the inputs of register 3 and register 7, the information inputs of which by this time are from the third and second; x outputs of block 1 are respectively time code and code; the divisor of justice, which determines the frequency of the 1-dap / h of the follower (the rate of change of the setpoint and the direction of change of the setpoint).

If in the third clock cycle from the first output of memory block 1 to the control input of counter 5, a unit arrives, then from the second output of memory block 1 to counter 5, a new setpoint value is output that is output to the device output V. In this case, in those bits of register 7, which control the counting direction, there must be zeros, if the setpoint change in counter 5 is changed when signals from the divider 4 output to the counting input of the counter 5 are received.

In the fourth cycle from the output of 6 pulses to the inputs of divider 4 and register 3 and one of the inputs of element 8, a pulse is received, which reduces the code in register 3 by one. The duration of the pulses of generator 6 is chosen less than ir; and the appearance of new information on the inverted outputs of register 3, In the same cycle, as the counting input of the reversible counter 3, the output of the frequency divider 4 produces a signal, the frequency of which is given by a code on the information inputs of the specified divider . Pulse signal increases or

decreases the setpoint value in a reversible counter 5.

The fourth clock cycle is repeated until the output of the registra overflow 3 times a unit,

which speaks of the end of the next tntner la aoemeni. On this signal, coming to the counting input of the register 2, its value increases by one unit, and at the address inputs

memory block 1 is set to the address of the next memory cell. The same signal through the element SHI 10 is fed to the input element 11.

Then the device goes to the second clock.

The operation cycle is completed when, after the next third clock cycle, in which the 3 register 3 times were received, the zero code of the end of cycle sign j in the fourth clock cycle enters all inputs; 5 elements and 8. This leads to the appearance at its output of a signal that passes through element I.SH 9 to the input of the reset of register 2. At the same time, a signal passes through the second element OR 10 to the exit of the element It. In the same way, in register 2 a zero code is set corresponding to the beginning of the control cycle, the device proceeds to the second clock cycle.

The device is stopped when a signal arrives at the input of the generator 6 residual rectangular impedance TbcoB from the device of the same name.

When the setpoint changes with a jump, the performance of the proposed device in comparison with the known one increases by as many times as the counting time by the reversible counter of the setpoint at maximum 11560064

the maximum frequency of the pulses and the output of the frequency divider is greater than the time of writing the specified setpoint into the counter.

ant / ck stop,

Claims (1)

A DEVICE FOR SOFTWARE REGULATION, containing a memory block, the address inputs of which are connected to the outputs of the address register, the first and second outputs - with the control and information inputs of the reversible counter, respectively, and the third outputs - with the information 'inputs of the time register, the count input connected to the generator output pulses and the counting input of the frequency divider, the inputs of the stop and start the device are connected to the corresponding inputs of the pulse generator, and the outputs of the reversible counter are the outputs of the device characterized in that, in order to improve the performance of the device, the task register is entered into it, the AND element, the first, the OR element and the second OR element and the first and second delay elements connected in series, the output of the first delay element is connected to the control input of the memory unit, and the output of the second delay element is with the control input of the job register, the information inputs of which are connected to the second outputs of the memory block, the first outputs are with the information inputs of the frequency divider, and the second outputs are controlled with the inputs I the counting direction of the reversible counter, by the counting input connected to the output of the frequency divider, the first and second inputs of the AND element are connected to the inverse outputs of the time register and the output of the pulse generator, respectively, and the output is connected to the first input of the first OR element, the output of which is connected to the address register reset input and the second input with the device startup input and with the first input of the second OR element, the second input connected to the overflow output of the time register and the counting input of the address register.