SU798844A1 - Digital object testing device - Google Patents

Description

(54) DEVICE FOR CONTROL OF DIGITAL OBJECTS

12

comparison, discriminator, number generator, signal generator address shaper and switch, the first output of the program storage unit connected to the first input of the number generator, the output of which is connected to the first input of the discriminator and to the first input of the switch, the output of which is connected to the second input of the discriminator, second output the program storage unit is connected to the first input of the cycle counter, the first output of which is connected to the first input of the address generator, the second, the input of which is connected to the second input the house of the comparison unit and the first output of the address counter, the second output of which is connected to the first input of the control unit, the first output of which is connected to the first input of the address counter, the second input of which is connected to the third output of the program storage unit, the fourth output of which is connected to the first input of the signal conditioner The second input of which is connected to the control output of the control unit, the second output of which is connected to the third input of the discriminator, the output of which is connected to the second input of the control unit, t The input of which is connected to the second output of the cycle counter, the second input of which is connected to the third output of the control unit, the fourth output of which is connected to the first input of the program storage unit, the fifth output of which is connected to the fourth input of the control unit, the sixth output of which is connected to the fourth input of the discriminator , the output of the signal conditioner is connected to the second input of a collator, the third input of which is connected to the output of the address conditioner, a frequency divider, a counter and an OR element are entered, the first input The frequency divider is connected to the seventh output of the program storage unit, the second input of the frequency divider is combined with the first input of the counter and the fifth output of the control unit, the fifth input of which is connected to the first output, the frequency divider, the second output of which is connected to the second input of the frequency generator and to the first input of the OR element, the third input of the frequency ramp. combined with the output of the c-equalizer, with the second input of the counter with the third input of the frequency divider and connected to the sixth input of the control unit, the seventh input It is connected to the third input of the counter, whose input is connected to the second input of the OR element and to the fourth input of the number generator, the output of the OR element is connected to the third input of the address generator.

Thus, by introducing the indicated nodes and links, the

programming possibilities and thus increasing the quality of control.

The drawing shows a block diagram of a device for controlling digital objects, such as LSI RAM.

The device contains a control unit 1, a program storage unit 2, an address counter 3 and a 4 cycle counter, a comparison block 5, a discriminator 6, a number generator 7, a signal generator 8, an address generator 9, a frequency divider 10, a counter 11, an element 12 OR and switch 13.

The control unit 1 has two-way communications with the storage units 2 -programs, counters 3, addresses and 4 cycles, discriminator 6, frequency divider 10 and counter 11. One of the outputs of control unit 1 is connected to the driver .. 8 control signals. The input of the Control Unit 1, connected to the inputs of the former 7 — the numbers of the divider 10 and the counter 11, is connected to the output of the comparison unit 5. Block

2 of the program has many connections with counters 3, addresses

and 4 cycles, a discriminator b, a shaper of 7. numbers, a shaper of 8 signals and a divider of frequency 10 with a programmable factor of -. neither Counters 3 and 4 are connected, respectively, to one and the other inputs of blocks 5 and 9. The first inputs of frequency divider 10 and counter 11 are combined and connected to the output of control unit 1, the second inputs of these nodes are also combined and connected to output of comparison unit 5. Output frequency divider 10 is connected to the first inputs of the former 7 numbers and the element 12 OR, and the output of the counter 11 - with the second inputs of these nodes. The output element 12 OR is connected to the input of the shaper address. The switch 1 is connected to the inputs of the discriminator 6 and the outputs of the formers 7-9,

The control unit 1 serves to coordinate the operation of units and units of the device when implementing various control algorithms (test sequences.) The control unit 1 consists of a programmable clock pulse generator designed to set a pulse following period and a synchronization device synchronizing the operation of counters

3 and 4 discriminators. 6, a frequency divider 10 with a programmable division factor and a counter 11.

Program block 2 is a set of H-bit memory registers (in our case it is intended for storing information necessary for executing programs for monitoring parameters of large integrated circuits of a random access memory (BIS RAM). This information contains information about realizable algo ; control rhythm (synthesis of necessary

test sequences) about the size of the controlled LSI RAM (i.e., the number of bits of the address) about the control area, the boundaries of which are the starting and ending addresses. about the duration of the period of synchronization pulses; about the values of the boundary values of the read signal O and 1 for the discriminator 6 j about the duration of control of the pulse of the .dl block 8 and their delay relative to the synchronization pulses; , about the order of information passing (direct or inverse to the inputs of the controlled LSI RAM. The information in the program block 2 can be entered from an electronic computer (computer or from the control panel / not shown}).

Counters 3 and 4 are N-bit binary counters (in our case, 16-bit counters}. The address 3 counter is designed to select a monitored memory cell and generate its address code, and the 4 cycles counter is used to count the number of cycles when implementing cyclic control algorithms, for example, running 1 or O, as well as for selecting the generation of the address code P., the cell when implementing the control algorithm reversible jump with variable pitch.

Block 5 of the cycle comparison is a set of digital comparators (according to the number of bits of counters 3 and 4) intended for bitwise comparison of binary codes received from the outputs of the bits of counters 3 and 4 and forming, when these codes are equal, a signal permitting the change of the address n - cells.

The discriminator 6 is an analog comparator with 4 input gates and an output. One of the comparators is designed to compare the amplitude of the output level with a predetermined reference level O, and the second with level 1. Logic elements I are designed to record the moment of comparison.

The shaper of 7 numbers is executed on D-triggers and logical elements AND and OR. The purpose of the generator is a 7-formation of a numerical code for the controlled BIS RAM. .

The driver 8 for control of two signals is made on a register, two digital comparators and two binary-decimal counters. It is intended to form pulses with a predetermined delay relative to the start pulse and with a given duration.

The address driver 9 is a decoder, inverters, and dual channel switch. Block 9 is designed to generate address cb

corresponding control cells according to a given algorithm.

The frequency divider 10 with a programmable division factor is an N-digit counter and is designed to set the number of accesses from the memory cell to the m - cell of the BIS RAM monitored, with the number of accesses equal to 1 -1.

Counter. 11 is a binary counter for generating the resolution of the memory memory monitoring.

Element 12 OR is intended to pass control signals to address generator 9.

The switch 13 for switching on the monitored object is a relay matrix that provides connection of the outputs of the monitored LSI RAM to the corresponding nodes.

The device works as follows.

In the switch 13 is placed controlled by the LSI RAM.

The Start signal from the program storage unit 2 sets the following signals at the outputs of control unit 1: permission signal for operation of the address counter 3, resolution of the formation of information recording signals by means of the control signal generator 9, blocking the passage of clock pulses to the counter of 4 cycles, a frequency divider 10 and a counter 11, and a permission signal for recording information from program storage unit 2 into nodes and units of the device. Upon receipt of this signal from program storage unit 2, the control program is entered into counters 3 and 4, into discriminator b, into drivers 7–9 and into frequency divider 10 with a programmable division factor. After entering the control programs from the program storage unit 2 to the listed nodes and blocks, the addresses of the Ps1m cells of the controlled BIS RAM are formed according to the implemented control algorithm.

When implementing the checkout algorithm, the chess order counter 3 addresses through the address generator 9 selects the memory cells of the controlled BIS RAM. The shaper 7 generates a numeric code that, by means of the shaper 8 control signals, is entered into the selected control cell, the device switches from recording mode to read information from the entire address field of the controlled BIS RAM.

In the implementation of the algorithm for controlling the treadmill 1 or O, the counter 3 of the address works in a similar way, and the counter of 4 cycles performs the counting

the number of cycles and generates a signal in binary code, which enters the comparison unit 5 and is compared in it with the binary codes of the address 3 counter.

If the specified codes are equal, the comparison block 5 generates a signal for the generator of 7 numbers to change the numerical information {direct or inverse) to the controlled BIS RAM. The same signal through the control unit 1 increases the content of the counter of 4 cycles per unit. At the same time, the contents of counter 3 address. does not change. The device is transferred to the information recording mode, the number generator 7 generates direct information recorded on the initial memory cell address, the control unit 1 enables the operation of the address counter 3, the contents of which increase by one, the comparison unit 5 again fixes the equality of the counter codes 3 and 4 the address of the second memory cell.

Inverse information is recorded in the second cell in a similar way, after which the device is again switched to read mode. Further, the device, when implementing the tracking 1 or O control algorithm, is performed in the described manner until the address code is set at the 4-cycle counter outputs. the final cell, which is fixed by the comparison unit 5, which generates a signal for the control unit 1, upon receipt of which the latter, after the end of the read mode, generates the termination control signal.

Prior to the implementation of the control algorithm, a variable step reversing jump by means of a signal from control unit 1 to set the memory cells of the monitored LSI RAM to the same initial state, a certain test sequence is applied to the inputs of the latter that provides this operation, after which the unit 1 control permits independent operation of counters 3 and 4. At the same time, counter 3 of addresses provides the choice of addresses n; memory cells, and the counter of 4 cycles - p memory cells controlled by the LSI RAM

Let, by the counter of 3 addresses, the address of the nj - control cell is selected, into which information is recorded by means of drivers 7 and 8 in accordance with the control program. Frequency divider 10, the division factor, which, given by software block 2, determines; the number of hits G (stepwise between, and No., j-control cells, generates a signal for the generator of 7 numbers, which, in turn, ensures the change of information in the controlled object (when addressing from I7.j-control cells) and in the discriminator b At the end of an access cycle equal to 1, frequency divider 10 generates a signal for control unit 1, which increases the content of the 4-cycle counter by one and thereby causes a transition to the control cell.

At the end of the cycle of accesses between h, -, and mi + t cells, in a similar HbDvi manner, a transition is made to m.j42. - cell, ect.

Thus, the information properties of the entire address field of the controlled BIS RAM are checked against the control cell.

The described process occurs until the comparison unit 5 fixes the equality of the digital codes of counters 3 and 4, which corresponds to nj m. At that, the comparison unit 5 generates a signal for the binary counter 11, which through the control unit 1 increases the content of the counter 4 cycles by one and thereby conditions the passage to. control cell Next, the information properties of the entire address field of the controlled BIS RAM are checked in a similar way with respect to the P - control cell.

When the control algorithm is implemented, a reverse jump with variable steps makes the choice of rtj it - control cells is arbitrary over the entire address field. The diagonal order control algorithm is a special case of it.

The proposed control device provides high quality control, completeness and reliability; makes it possible to diagnose faults in mass production, for example, LSI RAM, and, if necessary, in the event of a strong failure, to change the manufacturing technology in order to eliminate the cause of the failure.

Claims (2)

Invention Formula A device for monitoring digital objects comprising a control unit, a program storage unit, an address counter, a cycle counter, a comparison unit, a discriminator, a number generator, a signal generator, an address generator, and a switch, the first output of the program storage unit being connected to the first number generator input, output which is connected to the first input of the discriminator and to the first input of the switch, the output of which is connected to the second BJtpdy of the discriminator, the second output of the program storage unit is connected to the first input, The loop of the cycles, the first output of which is connected to the first input of the comparison unit and to the first / input of the address former, the second input of the KOTuporo is connected to the second input of the comparison unit and to the first output of the address counter, the second output of which is connected to the first input of the control unit, the first output of which connected to the first input of the address counter, the second input of which is keyed to the third output of the program storage unit, the fourth output of which is connected to the first input of the signal conditioner, the second input of which is connected to the control unit in & the control unit, the second output of the second is connected to the third input of the discriminator, the output of which is connected to the second input of the control unit, the third input of which is connected, the second output of the counterclock, the second input of which is connected to the third output of the control unit the last output of which is connected to the first input of the program storage unit, the fifth output of which is connected to the fourth input of the control unit, the sixth output of which is connected to the fourth input of the discriminator, the output of the signal conditioner is connected about. the second input of the switch, the third input of which is connected to the output of the address generator, in order to increase the reliability of the control, a frequency divider, a counter and an OR element are entered into the device, the first input of the frequency divider is connected with the seventh output of the program storage unit, the second input of the frequency divider is combined with the first input of the counter and with the fifth output of the control unit, the fifth input of which is connected to the first OUTPUT, the frequency divider, the second output of which is connected to the second input of the driver and to the first input of the OR element, the third input of the frequency driver is combined with the output of the comparison unit, with the second input of the counter, with the third input of the frequency divider and connected to the sixth input of the control unit, the seventh input of which is connected to the third input of the counter, the output of which is connected to the second the input of the OR element and with the quarter input of the number generator, the output of the OR element is connected to the third input of the address generator. Sources of information taken into account during the examination 1. USSR author's certificate No. 546838, cl. G 06 R 11/00, 1974. 2. Authors certificate of the USSR ,. 526954, cl. G 11 C 29/00, 1975. (prototype) „