SU1667079A1 - Signal checking device - Google Patents

Abstract

The invention relates to automation and computing and can be used in diagnostic systems for monitoring complex analog signals from control objects, as well as in debugging systems for analog-digital complexes. A distinctive feature of the device is that it allows a) to control the complex signals entering the device's input.

b) process the monitored signal in parallel

c) change the required accuracy of control

d) remember the magnitude and sign of the deviation of the signal level from the nominal value. The aim of the invention is to enhance the functionality by controlling the analog signals. The goal is achieved by introducing the switch 4, the counter 7, the analog-digital converter 8, the adder 9, the block 11 of the RAM, the element 12, the counter 13, the trigger 14, the element OR 15, the trigger 16, the clock generator 17, the element 18 , element OR 19, counters 20, 21, frequency dividers 5, 6. 2 Il.

Description

The invention relates to automation and computer technology and can be used in diagnostic systems for monitoring complex analog signals from control objects, as well as in debugging systems of analog-to-digital complexes.

The aim of the invention is to expand the functional capabilities by providing control of analog signals.

In FIG. 1 presents a functional diagram of the proposed device; figure 2 is a timing chart of his work. The device comprises a counter 1, a block 2 of constant firmware memory, a register 3, a switch 4, a first 5 and a second 6 frequency dividers, a counter 7, an analog-to-digital converter (ADC) 8, an adder 9, a comparison unit 10, a RAM block 11, , element And 12, counter 13, trigger 14, element OR 15, trigger V clock generator 17, element And 18, element OR 19, counters 20 and 21, trigger 22, a group of 23 inputs of the beginning of the controlled sequence, a group of 24 inputs of the beginning of the address records, a group of 25 inputs of analog signals, input 26 recording commands, input 27 start a, input 28 of the initial installation, a group of 29 outputs of the deviation of the controlled signals, outputs 30 and 31 of the device error.

There is a whole class of control objects, the functioning of which is accompanied by the delivery of complex analog signals characterizing their state to the external environment.

In this regard, for the control and diagnosis device, it is possible to set the task of analyzing and processing such complex analog signals.

The proposed device monitors such signals by pre-quantization of the time and level of memorization of the code of the current signal level at certain points in time;

comparing the code of the quantity U _T with the code of the reference value of the signal U ₃ in a given clock cycle;

setting the maximum accuracy of the correspondence of the codes Ut and and _е on the basis of programming in each step of the permissible deviation value Ut-U ₃ .

The device operates as follows.

At the initial moment of time, counter 1, first and second frequency dividers 5 and 6, counter 7, register 3, memory block 11, counter 13, triggers 14 and 16, counters 20 and 21, and trigger 22 are in the zero state.

At the output 2.1 of block 2 there is a single signal.

When applying a single signal to input 27 and to the installation input in ”1 of trigger 16, the latter is transferred to a single state. A single signal from the direct input of the trigger 16 is fed to the input of the clock generator 17 and turns it on.

A single signal The end of the command from the output 2.1 of block 2 is fed to the first input of the switch 4 and the control input of the counter 1. The initial address of the device is supplied to the group of information inputs 23.

The first clock from the first output 17.1 of the clock generator 17 passes through the switch 4 and is fed to the write enable input of counter 1. On the trailing edge of this clock, the address of the first microcommand of the device operation is written to counter 1.

The address signals of the first microcommand of operation of the device from the group of outputs of counter 1 are sent to the group of address inputs of block 2 and the second group of information inputs of block 11. At the same time, at the outputs of block 2, a microcommand of operation of the device appears, which is included in the control firmware of the 1st signal received at the input devices. In block 2, output 2.1 output End of command; group of outputs 2.2 - a field that carries information about the sampling interval of the signal over time; group of outputs 2.3 - a field that carries information about the result of quantization of a signal by level; output 2.4 - output that determines the counting of pulses by a reversible integrating counter 7; output 2.5- output Format indicator (used in case of a sharp jump in signal level); group of outputs 2.6 - a field that carries information about the permissible deviation of the signal received at the input 25 of the device from the reference signal stored in block 2.

Suppose that at a given time the signal does not undergo a level jump. Then, at the output 2.5 of block 2, there is a signal of the zero level, which is fed to the third inverse input of the 4th switch to the inverse control inputs of the first and second frequency dividers 5 and 6, causing them to trip. In addition, at the first input of switch 4, a zero signal is received. The end of the command is from the output 2.1 of block 2. The group of information inputs of the first frequency divider 5 receives information about the sampling interval over time of the signal from the first group 2.2 of the outputs of block 2. The group of information inputs of the second divider 6 frequencies you receive groups of 2.3 outputs of block 2 information about the quantization step of the signal by level. If the signal is currently increasing in level, then it is necessary to organize the counting of pulses by the counter 7 in the direction of addition. In this case, a single signal from the second output 2.4 of block 2 is supplied to the control input of the counter 7. In the event of a jump in the signal level, information about this level should be recorded in the counter 7. To do this, the device uses the concatenation procedure of two groups

2.2 and 2.3 outputs of block 2. These two groups of outputs of block 2 go to the group of information inputs of counter 7. Since the signal does not jump at a given moment of time, the zero signal from output 2.5 of block 2 goes to the control input of counter 7 and prohibits its operation group of information inputs.

On the trailing edge of the first clock coming to the counting input of the first frequency divider 5 from the first output

17.1 generator 17 clock pulses, is recorded in the first divider 5 frequency information about the sampling interval of the signal in time.

On the trailing edge of the first clock. received at the input of the expansion of the launch of register 3 from the second output 17.2 of the generator 17 clock pulses, information is recorded in it about the level of the signal received at the input of the device at a given time.

On the trailing edge of the same clock pulse received at the counting input of the second frequency divider 6, information is recorded in it about the step of quantizing the signal by level.

Suppose that at this point in time the signal has changed from zero to the level of one quantization step (i.e., one period of the device’s clock). Then, according to the second clock pulse, which arrives at the synchronization input of the second frequency divider from the second output 17.1 of the clock generator 17, an overflow signal appears at the output of the second frequency divider 6, which goes to the counting input of the counter 7 and puts it into a single state. In this case, information about the level of the signal that arrived at the input 25 of the device at a given time from the group of inputs of register 2 goes to the first group of inputs of the adder 9, and information about the level of the reference signal at a given time is supplied from the group of outputs of the counter 7 to the second group of inputs adder 9. Sum torus 9 subtracts codes of two signal levels. At the same time, information on the deviation of two levels appears on its group of outputs 9.1, which goes to the first group of information inputs of block 11 and the second group of inputs of block 10 of comparison. Information about the deviation sign comes from the output 9.2 of the adder 9 to the information input of the block 11.

The address where all this information is recorded in block 11. is set by the user on the group of 24 inputs of the device and is recorded in the counter 20. Information from the group of outputs of the counter 20 addresses goes to the group of address inputs of the block 11.

The deviation value of the two signal levels is compared. In the comparison unit 10, with the deviation value currently permissible.

If the permissible deviation is currently greater than the actual one, then a single signal appears at the output 10.1 of the comparison unit 10, which arrives at the first input of the first element And 12 and prepares it for operation.

The first clock from the third output 17.3 of the clock generator 17 is supplied to the second input of the first element And 12. A single signal from the output of the first element And 12 is fed to the reset input of the counter 13 and resets it.

If the permissible value is currently less than the actual value, then the output

10.2 block 10 comparison, a single signal appears, which is fed to the second input of the second element 14 and prepares it for operation.

The first clock pulse from the third output 17.3 of the clock generator 17 is fed to the first input of the second element And 18. At the same time, a single signal appears at its output, which is fed to the recording recording input of block 11 and records information on the value in it. not signal deviations, the sign of this deviation and the address of the micro-command, i.e. A place where two signals are not equal. In addition, a single signal from the output of the second element AND 18 enters the first input of the second element OR 19. A single signal from the output of the second element OR 19 enters the counting input of the counter 20 and redirects it. In addition, a single pulse from the output of the element And 18 enters the counting inputs of the counters. 13 and 21 and translates their single state.

Further, the device operates as described.

If the number of mismatches occurring in a row exceeds some predetermined value, an overflow signal appears at the output of counter 13, which arrives at the input of the installation in trigger G 14 and puts it into a single state. In this case, the device user receives information about the error at the output 30 of the device.

If the total number of mismatches exceeds some predetermined number, an overflow signal also appears at the output of counter 21, which is fed to the installation input in 1 ”trigger 22 and puts it into a single state. In this case, the user receives an error signal at the output 31 of the device.

When the device stops, three cases are possible. If the number of consecutive mismatches exceeds a certain value, then the overflow signal from the output of the counter 13 goes to the first input of the first OR element 15. A similar situation occurs if the total number of mismatches exceeds a certain value. Then the overflow signal from the output of the counter 21 goes to the second input of the first element OR 15. If the user himself wants to stop the operation of the device, then it is necessary to set the unit level at input 28, which goes to the third input of the first element OR 15. In all three cases, the signal is unit level from the output of the first element OR 15 goes to the reset input 0 of the trigger 16, which goes into the zero state. The signal of the zero level from the direct output of the trigger 16 is fed to the input of the generator 17 clock pulses and turns it off.

Claims (1)

Claim A device for monitoring signals, comprising a first counter, a read-only memory block and a register, wherein the bit outputs of the first counter are connected to a group of address inputs of a read-only memory module, characterized in that, in order to expand the functionality by providing control of analog signals, a switch is inserted into the device, two frequency dividers, four counters, an analog-to-digital converter, an adder, a comparison unit, a random access memory unit, three triggers, a clock generator, and the output of the end of the coma The unit of read-only memory is connected to the first control input of the switch, to the second inverse control input of the switch, to the third inverse control input of the switch and to the write enable inputs of the first counter, the output of the switch is connected to the counting input of the first counter, the group of outputs of the sampling interval of the read-only memory unit is connected to the group information inputs of the first frequency divider and the first group of information inputs of the second counter, the output of the first frequency divider is connected to the second information m is the input of the switch, the group of outputs of quantization of signals by the level of the permanent memory block is connected to the group of information inputs of the second frequency divider and the second group of information inputs of the second counter, the output of the second frequency divider is connected to the counting input of the second counter, the permission output of the summation of the constant memory block is connected to the resolution input the summation of the second memory block, the output indicator of the format of the permanent memory block is connected to the third information input of the switch, the input permission from the first frequency divider, the write enable input of the second frequency divider and the subtract enable input of the second counter, the group of outputs of the analog-to-digital converter is connected to the group of information inputs of the register, the group of outputs of which is connected to the first group of inputs of the adder, the group of bit outputs of the second counter is connected to the second group adder inputs, the group of outputs of the permissible deviation of the monitored signal of the read-only memory block is connected to the first group of inputs of the comparison unit, the output group the adder is connected to the second group of inputs of the comparison unit and the first group of information inputs of the RAM block, the information input of which is connected to the overflow output of the adder, the group of bit outputs of the first counter is connected to the second group of information inputs of the RAM block, the read permission input of which is connected to the zero potential bus devices, the equality output of the comparison unit is connected to the first input of the first AND element, the output of which is connected to the reset input at 0 of the third counter whose overflow output is connected to the installation input in ”1 of the first trigger and the first input of the first OR element, the output of which is connected to the reset input 0 of the second trigger, the output of which is connected to the start input of the clock generator, the first clock output of which is connected to the first information input the switch and the counting input of the first frequency divider, the second clock output of the clock generator is connected to the register enable input, with the counting input of the second frequency divider and the counting input of the second of the counter, the third clock output of the clock generator is connected to the second input of the first element And and the first input of the second element And, the second input of which is connected to the output of the inequality of the comparison unit, the output of the second element And is connected to the write enable input of the RAM block and the first input of the second element OR, the output of which is connected to the counting input of the third counter, the group of bit outputs of which is connected to the group of address inputs of the RAM block, the output of the second AND element is connected to the counting the input of the fourth counter and the counting input of the fifth counter, the overflow output of which is connected to the 20th second input of the first OR element and the installation input to 1 of the second trigger, the group of information inputs of the first counter is the group of inputs of the beginning of the controlled signals of the device, the group of inputs of the analog-to-digital converter5 is a group the inputs of the analog signals of the device, the group of information inputs of the third counter is a group of inputs for setting the device mode, the recording permission input of the third counter 1 0 is the input of the write permission of the device, the second input of the first OR element is the input of the initial installation of the device, the second input of the second element OR is' ^ the input of the write permission of the device command 15, the installation input to 1 of the first trigger is the device start input, the group of outputs of the RAM block is group of outputs of the deviation of the monitored signals, the direct outputs of the second and third triggers are the first and second outputs of the device error.