SU1674213A1 - Device for control of transport vehicle movement - Google Patents

Abstract

The invention relates to a device for controlling traffic and can be used to automatically control the speed of travel and the path traveled by the vehicle / vehicle /. The aim of the invention is to increase the information content of the device. With the beginning of the vehicle movement, a non-zero code appears at the output of the A / D converter corresponding to the speed of movement measured by sensor 3. Generator 1 is started. For each clock pulse, the speed values from the output of the ADC 4 enter blocks 5 and 9. In block 9, the distance traveled is determined by intensifying the measured speed over the interval ΔT (between two pulses of divider 2). In block 5, for each pulse of generator 1, the current speed value is compared with the stored one. Of the two values, a larger one is selected for the following comparison. By a pulse from the output of the divider 2, the values of V _max and S are periodically recorded in memory block 6, from where, via a command from the keyboard 10, they are fed through the converter 7 of the code to the indicator 8. 2 Cp f-ly, 6 ill.

Description

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The invention relates to a device for controlling the movement of vehicles and can be used to automatically control the speed of movement and the distance traveled by the vehicle.

The purpose of the invention is to increase the information content of the device by memorizing the maximum speed and the path traveled by the vehicle for several predetermined time intervals before stopping the vehicle.

FIG. 1 shows a functional diagram of the device; in fig. 2 - functional block diagram for determining the maximum speed; in fig. 3 - a functional block diagram of the memory; in fig. 4 is a functional diagram of the memory element; Fig. 5 is a functional block diagram for determining the distance traveled; in fig. 6 - the contents of the memory block.

The device contains 1 clock pulse generator, 2 frequency divider, speed sensor 3, analog-digital converter 4, maximum speed detection unit 5, memory block 6, code converter 7, indicator 8, distance path detection unit 9, keyboard block 10, keys 11-13, registers 14 and 15, comparator 16, delay elements 17-20, elements 21 1- 21 K of memory, registers 22 and 23, inverter 24, keys 25-29, delay elements 30-32, register 33, adder 34, keys 35-36 element 37 OR, elements 38 and 39 of the delay

Frequency divider 2 is designed to form at its output a sequence of pulses with a period multiple to the period of pulses at the output of generator 1. The period D t of the pulse following sets the time intervals, at each of which the maximum speed and the distance traveled S are determined.

Memory block G is designed to store certain values of VMSKC and S (Fig. 6). The number K of memory elements 21 determines the number of memorized values of Umakg and S

The device works as follows

With the onset of vehicle movement, a signal appears at the output of sensor 3, which is converted by analog-to-digital converter 4 into a digital code

When a non-zero code appears at the output of the analog-digital converter 4, the generator 1 is turned on (Fig. 1) The pulses from its output go to the clock inputs of the maximum speed determination unit 5 and the path measuring unit 9 and the divider 2 input. For each clock pulse, the speed values from the output of the sensor 3 through the Converter 4 is fed to the information inputs of blocks 5 and 9.

In block 9 determining the distance traveled

S value is determined by integration

speeds on the time interval At (between

two pulses from the output of the divider 2).

In the block for determining the maximum

speeds for each clock pulse of generator 1, the current speed value is compared with the previously memorized one. Of the two values for the following comparison, in block 5, the maximum

By a pulse from the output of divider 2, the value of / max and S is rewritten into memory block 6, from which, using a command from the keyboard 10, can be displayed on indicator 8.

At the same time, when a signal appears corresponding to value 1. On one of the control inputs of generator 1, trigger 1-3 is transferred to state 1 and the control signal from the trigger through AND circuit 1-4 will open the output of clock generator 1-1 С of generator 1 the pulses are transmitted to key 11 of block 5, to key 35 of block 9, as well as to delay elements 18 39, 30 and 32, blocks 5, 9 and 6,

Code of the number corresponding to the speed

Vi at time ti (Fig. 6) through the key 11 enters the register 14 and further into the comparator 16. In addition, this code enters the input of the key 12. Since the O code is originally written in register 15, then its output

according to the signal from the output of divider 2; according to the Vits code of the number corresponding to the value O. This value is transmitted to comparator 16, where it is compared with the value of VOR Since Vi 0, then the output of comparator 16

Wits a signal that opens / opens the key 12 and the value Vi is written to register 15. Write permission comes from comparator 16 through delay element 17

If at the next time moment ti2 value / 2 Vi, then the code corresponding to the value / 2 is written to register 15. Otherwise (V2 $ Vi) at the output of the comparator 16, there will be no signal in the register

After this, the speed at the times tn 112, tn where n is the division factor of divider 2 in the first interval D ti at the output of block 2, will be stored in this register.

signal is generated This signal initially opens key 13, and then through delay element 20 a signal is generated to read the contents of register 15 into memory block 6 After reading the code through the key

Delay ment 13 This signal zeroed the register 15.

The code of the number corresponding to Vi from converter 4 is fed to the inputs of the key 35 and the delay element 17 of the block 9. When the key 35 of the pulse arrives at the second input from the generator 1, the value Vi is entered into the adder 34. To the second input of the adder 34, the signal from the element 37 OR a second term is read from register 33. In the adder 34, Vi + 0 is added and the content is transferred to the register 33. The code enable signal from the register 33 is received from the generator 1 through the delay element 39. Since in the adder 34 there is an output register of results, then at its output before the next measurement there will be a code of the previous value.

At the time point tin (p. 5), at the output of divider 2, a signal is sent via Wits, which will open the key 36 and the contents of register 33 by the read signal of element 37 OR will go to memory block 6 In addition, with a delay determined by delay element 38, the signal will reset register 33 to the zero state, and reset adder 34.

Thus, the output of block 9 will form a code number corresponding to the value.

S Vi At + V2 At + ... - Vn At.

The number codes / Max and S are entered into registers 22 and 23. respectively, of the first element 21.1. When changing imax i. 5, at the second interrupt At2, these values also go to registers 22 and 23. However, before writing these values, the divider 2 signal reads their contents through the open signal from the inverter 24 keys 28 and 29. From the registers 22 and 23 of the element 21.1, VMBKC and S are written Registers 22 and 23 of the second element 212. When measuring Umax and S on the third interval At, the contents of the memory element 21.2 are rewritten into the element 21.3, the element 21.1 - into the element 21.2, and the new value is entered into the memory element 21.1.

If it is necessary to read data, a signal is given from the keyboard 10 to the input of unit 6. At the input of the element 21.K, a read signal is generated. This signal opens keys 26 and 27 and reads data from registers 22 and 23 through element 25 OR. In addition, the keys 28 and 29 are closed using an inverter 24.

The 7max and 5b-k values are fed to the code converter 7 and further to the indicator 8.

When stopping the vehicle on all outputs of the converter 4 will

O signal, which will prohibit the operation of the generator 1. The operation of the device will stop there.

Claims (3)

1. Motion control device vehicle containing a speed sensor and an indicator that is different. that, in order to increase the information content of the device, an analog-digital converter, a clock pulse generator, a frequency divider, a maximum speed determination unit, a path determination unit, a memory block, a code converter, a keyboard block, 5, the output of the speed sensor is connected to the input of an analog-digital converter, the output group of which is connected to the information inputs of the path determination unit, the maximum speed determination unit and the control inputs of the clock generator, the output of which is connected to the clock inputs of the memory unit, the maximum definition unit speed, a block for determining the past path and a frequency divider, the output of which is connected to the control inputs of the memory block, the block for determining the maximum speed and the block edeleni distance traveled, the group whose outputs 0 is connected to the first group of information inputs of the memory unit, the group of outputs of the maximum speed determination unit is connected to the second group of information inputs of the memory unit, the outputs of which 5 through a code converter connected to an indicator, the outputs of the keyboard unit are connected to a group of control inputs of the memory unit. 2 device pop. 1, characterized in that the maximum speed determination unit contains three keys, two registers, a comparator, four delay elements, the information inputs of the first key are information inputs of the block, the control input of the first key and the inputs of the first delay element are combined and are a clock input block, the outputs of the first key are connected to the group of information inputs of the first register. 0 group of outputs of which is connected to the first group of inputs of the comparator and to the group of information inputs of the second key, the group of outputs of which is connected to the group of information inputs of the second register, the group of outputs of which is connected to the group of information inputs of the third key and to the second group of inputs of the comparator whose output is connected with the control input of the second key and with the input of the second delay element, the output of which is connected to the resolution enable input of the second register, the output of the first delay element is connected to the input the recording resolution of the first register, the inputs of the third and fourth delay elements and the control input of the third key are combined and are the control input of the block, the output of the third delay element is connected to the zero input of the second register, the output of the fourth delay element is connected to the read permission input of the second register, the output group The third key is a group of block outputs. 3. The device according to claim 1, wherein the path determination unit comprises a register, two keys, an adder, two delay elements, an OR element, a control input of the first key combined with an input of the first delay element and is a clock input of the block the output of the first delay element is connected to the input permitting a register entry whose output group is connected to a group of information inputs of the second key and the first group of information inputs of an adder, the group of outputs of which is connected to the group of information inputs of the register, the control input of the second key, the input of the second delay element and the first input of the OR element are combined and are the control input of the block, the remaining inputs of the OR element are combined with the information inputs of the first key and are the information inputs of the block , group of information outputs of the first key connected to the second group of information inputs of the adder, the output of the element OR is connected to the input of the register read resolution, the output of the second delay element is connected to the inputs of zeroing the adder and the register, the group of information outputs of the second key is the group of information outputs of the block. FIG. 2 Fke.Z FIG. four 2 / FIG. five FIG. 6