SU1649684A1 - Video signal amplitude regulating device - Google Patents

Abstract

The invention relates to television technology. The purpose of the invention is to reduce the time to stabilize the amplitude of the video signal. The device contains a clock pulse generator 1, matching amplifiers 2, 3 and 4, an image sensor 5 on a device with a predetermined connection, a video amplifier 6, a mismatch sensor 7 consisting of level 8 and 9 detectors, an OR 10 element, D-triggers 11 and 12, element 13, reversible counter 14, accumulation time control unit 15, compiler 16 codes made on ROM, RS-flip-flop 17 delay unit 18, line (or frame) countdown unit 19, and end of line (or frame) pulse generator 20 By changing the code obtained at the output of block 15 By sequentially changing the code of the reversible counter 14 supplied to the address inputs of the block 15, the moment of applying voltage to the sensor 5 is controlled. Since the moment of removing this voltage is synchronized with the end of the line (or frame), the code change at the output of the block 15 regulates accumulation time and, consequently, the amplitude of the video signal 4

Description

The invention relates to television technology and can be used in television tracking systems.

The aim of the invention is to reduce the stabilization time of the amplitude of the video signal.

FIG. Figure 1 shows the structural electrical circuit of the video signal stabilization device; in fig. 2 - 4 are timing diagrams for the operation of the device.

A video amplitude stabilization device contains a clock pulse generator 1, matching amplifiers 2 and 3, 4, an image sensor 5 on a device with a given link (CCD), a video amplifier 6, an error sensor 7 containing level detectors 8, 9, the element OR 10, the first and the second D-flip-flops 11, 12, element And 13, reversible counter 14, accumulation time control unit 15, performed on ROM, code comparator 16, RS-trigger 17, delay unit 18, countdown unit 19 of the row (or frame) length, driver pulse 20 end of line (or frame).

The device for stabilizing the amplitude of the video signal works as follows.

The amplitude of the video signal is controlled by changing the accumulation time. The accumulation process ends at the end of the frame and occurs at the moment of arrival of the end of a line or frame from pulse generator 20 to the RS flip-flop 17

O 4 S O 00 4

The beginning of accumulation occurs at the moment of coincidence of the current code of reference block 19, arriving at the first input of the Iodine comparator 16, with the code presently present at the output of the control block 15 of accumulation time, arriving at the second inputs of the comparator of codes 16.

Thus, by changing the code presented at the output of the control unit 15 by successively changing the code of the reversible counter 14 supplied to the address inputs of the control unit 15, the voltage applied to the image sensor 5 is regulated, and since the moment of relieving this voltage synchronized with the end of the line (or frame), then the code change at the output of the control unit regulates the accumulation time and, consequently, the amplitude of the video signal.

The NI codes recorded in the neighboring cells of the ROM 15 differ in the step size of the control D NI, which, for example, can be determined by the formula

Lm | M | K, where K is the code change coefficient;

NI - the value of the code recorded at the i-th address of the ROM 15.

Consider the case when the amplitude of the video signal during a row (or frame) exceeds the specified upper value Hi (see Fig. 2),

At time ti, the amplitude of the video signal at the output of video amplifier 6 (see Fig. 2a) exceeds the specified lower value, a level detector 9 will be triggered, from the output of which the C-input of D-flip-flop 11 receives a pulse, the front of which is recorded but present at the D input.

From the direct output of D-flip-flop 11 (see Fig. 2c) a logical unit will arrive at the control input of the reversible counter 14, which will establish a positive counting direction. At time t, the amplitude of the video signal at the output of video amplifier 6 (see Fig. 2a) exceeds the set value Hi, the level 8 detector, from the output of which to the C input of D-flip-flop 12 through the OR element, will trigger (see Fig. 2e) there will be a pulse, the front of which records the logical unit constantly present at the D input (see FIG. 26), since the second input of the element I 13 during the whole frame from the inverse output of the imaging unit 20 (see Fig. 2e) signal is a logical zero, then from the output of the element And 13 to the first input of the element OR 10 also comes

the signal is a logical zero, hence a positive pulse received at the second input of the element OR 10. According to its output.

From the output of the D-flip-flop 12 (see Fig. 26) on

the counting input of the reversible counter 14 will receive a positive impulse, on the front of which an increase in the code of the reversible counter 14 by one will occur. C code

0 output of the counter 14, arriving at the address inputs of the ROM 15, will lead to a change in the code determining the accumulation time. A new code corresponding to a shorter accumulation time will come from the output of ROM 15 to the second input of comparator codes 16.

If the amplitude of the video signal exceeds the upper preset IC level earlier than the ROM accumulation section is turned on, the error correction takes place within the same frame, if later, the change of the code determining the accumulation time will not lead to the correction and will be implemented in the next frame ( see Fig. 2g), if the amplitude of the video signal during

5 lines (or frames) will be within the interval between the upper and lower setpoints (see Fig. 3), only the level 9 detector will be triggered, by means of which D-flip-flop 11 will write the logical

0 unit. The logical unit is written to the D-flip-flop 12 on the front of a positive pulse arriving at the C input from the output of the element OR 10. Since the level 8 detector does not work, then

5 the current of the line (or frame) to the second input of the element OR 10 will always receive a logical zero. And during the line (or frame) to the second input, the element And 13 with the inverse output of the imaging unit 20 (see

0 figs, back) will be a logical zero. WITH

time ti (see Fig. For) at first

input from the reverse output of D-flip-flop 11 (cm,

FIG. So) there will be a logical zero.

- Consequently, until the arrival of a negative pulse from the output of the delay block 18 (see Fig. 3g) to the R inputs of D-flip-flops 11 and 12, setting their direct outputs to zero (see Fig. Sv, b) , at the first input of the element OR 10 s

0 output element And 13 will receive a logical zero and D-trigger 12 will not work. Accordingly, the code of the reversible counter 14 will remain unchanged and no correction will occur (see FIG. 3).

5If the amplitude of the video signal during a row (or frame) does not exceed the specified lower value (see Fig. 4a), level 8 and 9 detectors do not work, and D-flip-flops 11 and 12 will remain in the initial state (see Fig. 4 c, b). Direct output

D-flip-flop 11 (see FIG. 4c) a logical zero signal will be applied to the control input of the reversing counter 14, which will establish a negative counting direction.

From the inverse output of the D-flip-flop 11 to the input of the element And 13 a logical unit will arrive. At the moment of arrival of the positive impulse of the end of the line (or frame) from the inverse output of the former 20 (see. Fig. 4e) to the input of the element And 13, from its output to the input element OR 10 positive pulse, and since the output of the level detector 8 to the second input of the element OR 10 receives a logical zero, this pulse from the output of element 10 (see Fig. 4e) goes to the C-input of D-flip-flop 12. Positive edge the pulse is recorded logical unit, constantly at the D-input.

From the direct output of D-flip-flop 12 (see Fig. 46), a positive impulse will be sent to the counting input of the reversing counter-4 and the code of the reversible counter 14 will decrease by one. The code from the output of the reversible counter 14, arriving at the address inputs of the ROM 15, will lead to a change in the code determining the accumulation time. A new code corresponding to a longer accumulation time will come from the output of ROM 15 to the second input of comparator codes 16, which in the next frame will increase the amplitude of the video signal (see Fig. 4g). Then, a negative pulse, arriving at the P input of the D-flip-flop 12 from the output of the delay block 18 (see Fig. 4d), will set it to its initial state.

Claims (1)

Claims of the invention A device for stabilizing the amplitude of a video signal, comprising a generator of so-called pulses, n outputs of which are connected to the inputs of the corresponding matching amplifiers whose outputs through an isobuseum sensor connected in series on a charge-coupled device (CCD) and a video amplifier connected to the input of the error sensor, the first output of which is connected to the C input of the first D-flip-flop, the inverse output of which is connected to the first input of the And element (n + 1) the output of the clock pulse generator is connected to the input of a block of reference for the duration of a line, 0 one of the outputs of which is connected to the input of the pulse terminator of the end of the line, the inverse output of which is connected to the R-input of the RS flip-flop, whose S input is connected to the output of the code comparator, to 5 one of the inputs of which are connected to the corresponding outputs of the block of the reference line length, and the output of the RS-flip-flop is connected through (n + 1) matching amplifier with the corresponding sensor input 0 images on the CCD, as well as a reversible counter and a second D-flip-flop, characterized in that, in order to reduce the stabilization time of the amplitude of the video signal, the control unit is inserted into it 5 accumulation time, the OR element and the delay unit, while the reversible counter outputs the accumulation time control block connected to the corresponding inputs of the code comparator, the forward output of the second D-flip-flop is connected to the counting input of the reversible counter, and the C output input of the OR element , to one of the inputs of which the output of the element I is connected, and to the other input of the element 5 OR the second output of the error sensor is connected, the R inputs of the first and second D-flip-flops are connected to the output of the delay unit, the input of which is connected to the direct output of the line terminator, 0 whose inverse output is connected to the input of the I element, and the forward output the first D-flip-flop is connected to the control input of the reversible counter. 1 gpf fr896Wl and ffl Uz and BUT i f Change code t Ni .f FIG. four