SU1453620A1 - Video signal amplitude stabilizing device - Google Patents

Abstract

The invention relates to television. The purpose of the invention is to increase the accuracy of stabilization. The device contains Mr. I clock pulses, matching amplifiers 2, sensor 3 images on the device with charge St. -. Zyo, counter 4 count the length of the line (frame), shaper 5 pulse. end of line (frame), matching amplifier 6 photo.sensitive sections, video amplifier 7, mismatch sensor 8, D-flip-flops 9, RS-trigger 10, reversible counter 11, el-I 12, comparator 13 codes, register 14, shapers 15 short pulses, shaper 6 pulses and filter 17 HiDKHHx frequencies. The goal is achieved by decreasing .i and establishing a stable video signal level. 4 il.

Description

are united with the R-inputs of the first rf of the second 20 D-flip-flops.

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Claims (1)

25 Formula of the invention A video signal amplitude stabilization device containing η matching amplifiers, a 30-pulse clock generator, a charge-coupled image sensor (CCD) in series, the corresponding clock inputs of which are connected through the corresponding η matching 35 amplifiers to the first outputs of the clock, and the video amplifier is connected in series connected by an RS.trigger and matching amplifier of the photosensitive section, 40 output of which is connected to the control input of the image sensor on the CCD, connected in series with a counter for counting the length of the line (frame), the input of which is connected to the second output 45 of the clock generator, and a comparator of frames, the output of which. connected to the S-input of the RS-flip-flop, a pulse shaper of the end of the line (frame), the input of which is connected to the 5Q second output of the counter for counting the length of the line (frame), and the first output is connected to the R-input of the RS-flip-flop, a reverse counter, element And, the output of which is connected to the subtraction input 55 of the reverse counter, the mismatch sensor, the first and second D-flip-flops, the C-inputs of which are connected respectively to the first and second output of the mismatch sensor, R-inputs 7) 453620 are combined and connected to the first output of the end-of-line (frame) pulse former, and the D-inputs are inputs of a logical unit level setting, characterized in that, in order to increase stabilization accuracy by reducing the time to establish a stable video signal level, a register, signal the inputs of which are connected to the outputs of the reversible counter, and the outputs are connected to the second inputs of the code comparator, N shapers of short pulses, the inverse outputs of which are connected to the inputs of the element And, (2N-2) D-flip-flops, C- passages are connected with similar outputs the error detector, R-inputs are combined with the R-inputs of the first and the second 20 D-flip-flops and the control input of the register, D-inputs are inputs of setting the level of a logical unit, ₅ low-pass filter, the input of which is connected to the output of the video amplifier, and the output is connected to the input of the mismatch sensor, a pulse shaper, the first input of which is connected to 10 second output of the shaper pulse of the end of the line (frame), the second input is connected to the third output of the clock generator, the third inputs are connected to the outputs of i ~ x 15 D-flip-flops, where i = N + l, 2N, and the output is connected to the summing input of the reverse counter, at The inputs of the short-pulse shapers are connected to the outputs of the same D-flip-flops.