SU1277426A1 - Device for stabilizing amplitude of video signal - Google Patents

Abstract

The invention relates to television technology and can be used in measurement systems built on the basis of cameras on devices with charge coupling. The purpose of the invention is the expansion of the dynamic range of the amplitude control of the video signal. The device contains a clock pulse generator 1, a matching amplifier 2 of the output register, a matching amplifier 3 of the memory section, a matching amplifier 4 of the photosensitive section, an image sensor 5 on a charge-coupled device, a video amplifier 6, a voltage comparator 7, a frequency divider 8, a block 9 counts of the length of the line and frame, shaper 10 pulses of the end of the line and frame, comparator 11 codes, reversible counter 12, RS flip-flop 13, two elements And 14. and 20. The goal is achieved by introducing a counter 15 pulses, the element OR 21, two additional RS-flip-flops 17 and 16i of two additional compilers 19 and 18 codes. 2 Il. Yu "-sj 4 to Oh

Description

The invention relates to television technology and can be used in measuring television systems built on the basis of cameras on devices with a CCD charge coupling. The purpose of the invention is to expand the dynamic range of the amplitude control of the video signal. FIG. 1 presents a structural

electrical circuit of the video signal amplitude stabilization device; in fig. 2 - temporary 1e diagrams, based on the operation of the video signal amplitude stabilizer.

The video signal amplitude stabilization device includes a clock pulse generator 1, a matching amplifier 2 of the output register, a matching memory amplifier 3 memory section, a matching amplifier 4 of the photosensitive section, a CCD image sensor 5, a video amplifier 6, a frequency comparator 7, a divider 8 frequency unit 9 counts of the length of the line and frame, shaper 10 pulses of the end of the line and frame, comparator 11 codes, reversible counter | 2, RS flip-flop 13, second element I 14, counter 15 pulses, second additional RS trigger 16, the first complement flax RS-trigger 17, a comparator 18, a first additional code second supplemental code comparator 19, the first AND gate 20, an OR gate 21.

The device works as follows.

The clock pulse generator 1 generates control signals for the matching output amplifier of the 2-output register, matching amplifier 3 of the memory section, matching amplifier 4 of the photosensitive section, control pulses of the 9-unit reading unit of the line and frame lengths and frequency divider B, frame damping pulses (Fig. 2a), incoming to the input of the driver 10 pulses of the end of the line and frame, the input element OR 21.

The unit 9 for counting the length of a line and a frame forms a parallel code arriving at the second inputs of the comparator 11 codes, as well as the damping receiver mix (Fig. 2 $) entering the input of the imager 10 pulses of the end of the line and frame.

Shaper 10 pulses end of line n frame generates pulses

razheni The pulses come from the second output of the output register amplifier 2 to the input of the second element I 14.

The video signal from the output of the image sensor 15 on the CCD through the video amplifier 6 is fed to the input of the voltage comparator 7, to the second input of which a reference signal is applied (Fig. 2e). When the video signal level of the reference signal is outputted at the output of the comparator 7, the logic unit level signal is outputted (Fig. 2e1) arriving at the first input of the second element I 14, the second input of which receives the pulses of the matching amplifier 2 of the output register (Fig. 23). And 14 at the first input of the pulse counter 15 pulses arrive, the number of which is equal to the number of CCD elements, the video signal from which exceeds a predetermined threshold level (Fig. 2p. Pulses at the end of the line and frame (Fig. 26), arriving at the second the input of the pulse counter 15 at the end of the line and the frame resets the pulse counter 15. The pulses of the end of the frame (Fig. 2d) set the RS-flip-flops 13, 16, 17 to the zero state. From the outputs of the pulse counter 15 pulses the binary parallel code is fed to the first inputs additional code comparators 18 and 19. The second inputs of the additional comparator 18 are given a code of the number equal to the number of defective image points, the video signal from which exceeds the reference signal, and the second inputs of the additional comparator 19 have the number equal to the sum of the number of numbers Twa defective image points and the allowable number of pixels, the video signal from which can exceed the reference signal level.

If the number of pixels per line or frame, the video signal from which exceeds the threshold level, is greater than the number recorded in the additional comparator at the end of the line and frame (Fig. 2b) arriving at the input of the counter 15 IC pulses, the pulses at the end of the frame (Fig. 2t) received at the R input of the RS flip-flops 13, 16, 17. The Vcod register matching amplifier 2 generates control pulses of the output register of the image sensor 5 (Fig. 23), each pulse corresponding to an element of the 18 code but less than the number written to the comparator 19 codes, a pulse appears at the output of the code comparator 18 at time t (Fig. 2i), setting the direct output of the additional RS flip-flop 16 to the state of the logical unit (Fig.2l) On, the output of the additional RS flip-flop 17 the logical zero state remains (Fig. 2m). At the output of the first element I 20, the output of the element ШШ21 (Fig. 2n) is the state of the logical unit that prohibits the counting of pulses by a reversible counter 12. During a frame extinguishing pulse, the code at the output of the reversing counter 12 does not change and the charge accumulation time remains the same (Fig. 2o, T T)

If, during a row or frame, the number of elements, the video signal from which exceeds the reference signal, is greater than the numbers recorded at the second inputs of the comparators 18 and 19, then at times t and t, pulses appear on the output of the latter (Figs. 2i, k) the direct outputs of the additional RS-flip-flops 16 and 17 establish the state of the logical unit (Fig. 2L, m), and on the inverse output of the additional RS-flip-flop 17, at the output of the first element AND 20 and during the frame extinguishing pulse at the output of the element OR 21 (FIG. 2n) a logical zero state is set. A reversible counter 12, controlled by the second input from the output of the additional RS flip-flop 17, begins to work on addition and its code is increased by the number determined by the number of pulses generated by the frequency divider 8 and fed to the input of the reversible counter 12. The parallel binary code arrives from the output of the reversible counter 12 to the first input of the comparator 11 codes, the second input of which receives a parallel binary code from the output of block 9 of the reference length of the string and frame. When the codes from the output of block 9 of the length of the string and frame and the reversible counter 12 coincide, the pulse from the output of the comparator 11 codes sets the RS flip-flop 13 to the state of logical one. As the code is increased on the reversing counter 12, the accumulation time is reduced (Fig. 2o).

If during a row or frame the number of elements, the video signal with

which, exceeds the threshold level, is less than the numbers recorded on the second inputs of additional comparators 18 and 19 codes, the latter do not work, the logical output zero remains at the direct output of additional RS-flip-flops 16 and 17 (Fig.2l m). At the output of the element OR 21, during the frame damping pulse, the state of a logical zero (Fig. 2n) is set and a reversible counter 12, controlled by the first input from the output of the additional RS flip-flop 17, works on subtraction, and the accumulation time of the charge increases (Fig. 20, T T,).

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Claims (1)

Invention Formula A video amplitude stabilization device comprising a series-connected pulse generator, an output register matching amplifier, an image sensor on a charge-coupled device (CCD), a video amplifier whose output is a device output, and a voltage comparator whose second input is an input the reference signal, the matching amplifier of the memory section, connected between the second output of the clock generator, and the second input of the image sensor on the CCD, the third input of which is connected via photosensitive amplifier. section with the third output of the clock pulse generator, the fourth output of which is connected to the input of the block of length and frame length reference and to the input of a frequency divider, the output of which is connected via a reversible counter to the corresponding first inputs of the code comparator, the second inputs of which are the length of the line and the frame, the second output of which is connected to the first input of the pulse generator at the end of the line and frame, the first output of which is connected to the R input of the RS flip-flop, the S input of which It is connected to the output of the code comparator, and the output of the RS flip-flop is connected to the second input of the matching amplifier of the photosensitive section, the first and second elements AND, characterized in that, in order to expand the dynamic range of adjusting the amplitude of the video signal, a pulse counter is entered into it, OR , two additional RS-flip-flops, two additional code comparators, with the fifth output of the clock generator connected to the combined second input of the end-of-line and frame pulse former and the first input of the e OR, the second input of which is connected via the first element AND to the inverse output of the first additional RS flip-flop, the direct output of which is connected to the second input of the reversible counter, the third input of which is connected to the output of the OR element, the output of the voltage comparator is connected to the first input of the second element And, the second input of which is connected to the second output of the matching amplifier of the output-, 12 266 th register, and the output is connected to the information input of the pulse counter, the reset input of which is connected to the output of the pulse shaper ca end of the line and frame, and the outputs of the pulse counter are connected to the combined inputs of the first and second additional code comparators, the outputs of which are connected respectively to the S inputs of the second additional RS first and triggers, the combined R inputs of which are combined with the R input of the first RS trigger, and the output the second additional RS-flip-flop is connected to the second input of the first element And, the second inputs of the first and second additional Comparators codes are connected to the corresponding inputs of the reference codes.