SU1275788A1 - Device for automatic stabilizing of amplitude of video signal - Google Patents

Description

an OR-NO 28 element and two D / A converters 30 and 31. With this combination of device elements, the presence in the video signal of the geometric noise of sensor 5, as well as the presence of noise and pulsed fluctuations of the video signal, do not result in a device tuning by emission level. This increases the accuracy of the device when changing the backlight and the spatial frequency of the transmitted image. Claims 2 and 3 of the formula give examples of the performance of BS 21, -22 and 23, and LB 26. 2 cf f-crystals, 5 ill.

1. The invention relates to the transmission and analysis of images using video signal sensors on devices with charge-coupled communication (CCD) and can be used, in particular, in television technology and in automation. The aim of the invention is to improve the accuracy of stabilization of the amplitude of the video signal. Figure 1 shows the structural electrical circuit of the device; Fig. 2 is a structural electrical circuit of the comparison unit; on fig.Z structurally electrical circuit of the logic unit; Figures 4 and 5 are voltage diagrams at various points of the device. A device for automatically stabilizing the amplitude of a video signal contains a generator of 1 clock pulses,. output register matching amplifier 2, memory section matching amplifier 3, accumulation section matching amplifier 4, video signal sensor 5 on a charge coupled device (CCD), video amplifier 6, first voltage comparator 7, frequency divider 8, length reference unit 9 line and frame, pulse shaper 10 end of line and frame, comparator 11 codes, first reversing counter 12 RS flip-flop 13, adjustable amplifier 14, differential amplifier 15, second and third comparators 16 and 17 voltages, second element AND 18 first element OR 19, first And 20, the second, third and first blocks 21-23 of comparison, the second and third reversible counters 24 and 25, the logical block 26, the second element OR 27, the element SH1I-NO 28, the third element OR 29, the first and second digital channels converters (D / A converters) 30 and 31. The comparison unit contains a counter of 32 pulses, comparators 33 and 34 codes, RS flip-flops 35 and 36, and element 37. The logic block contains elements OR 38 and 39, elements AND-NOT 40 and 41, and elements NOT 42 and 43. The device operates as follows. The generator 1 supervises the control signals for matching amplifiers 2, 3 and 4, the control pulses of the block 9 and the frequency divider 8, frame damping pulses (Fig.4, 5a) received at the second input of the driver 10 of the end of line and frame, the second input of the second the element OR 27 and the third input of the logic unit 26. The block 9 forms a parallel code arriving at the first inputs of the comparator 11 codes, as well as the quenching mixture of the receiver (Fig.45) arriving at the first input of the imaging unit 10. The imaging unit 10 generates pulses of the end of the line and frame (figure 4 (), by Stepping on the second inputs of the comparison blocks 21-23, the end of frame pulses (Fig. 4d) arriving at the R input of the RS flip-flop 13 and the fourth inputs of the comparison blocks 21-23. The matching amplifier 2 generates control pulses of the output register (Fig. AE ), which come from the second output of the matching amplifier 2 to the second inputs of the elements AND 18 and 20, the second input of the element OR 19, and each imputoc corresponds to the image element of the CCD matrix. . The parallel binary code is fed from the output of the reversible counter 12 to the second input of the comparator 11 codes, the first input of which receives the parallel binary code from you-; block 9. When the codes from the output of block 9 and the reversible counter 12 coincide, a pulse of coincidence with the output of the code comparator 11 sets the RS flip-flop 13 to the state of logical one. The end-of-frame pulses (Figure 4) set the RS flip-flop 13 to the logical zero state. The charge accumulation time of the video signal sensor 5 on the CCD is determined by the code at the output of the reversing counter 12. As the code at the output of the reversing counter 12 increases, the accumulation time of the charge decreases, and decreasing the code increases to T T (Fig; 4p), defined as the maximum accumulation time of the charge. The video signal from the output of the sensor 5 through the video amplifier 6 is fed to the first input of the voltage comparator 7 to the second input of which is supplied Unopi rational signal (Fig. Ae). When the video level of the reference signal Upop is exceeded at the output of the comparator 7, the signal of the level of the logical unit is outputted (Fig. Attack to the first input of the AND element 20, the second input of which receives impulses from the matching amplifier). Output register 2. From the output of the element I 20, the third input of the third comparison unit 23 receives pulses, the number of which is equal to the number of CCD elements, the video signal from which exceeds the specified threshold level (Fig. 4p). The first input of the comparator unit 23 is given a code of a number equal to the number of defective pixels, the video signal from which exceeds the reference signal (Fig. 4e), and the second input of the comparator unit 23 is supplied with a code of a number equal to the allowable number of pixels, the video signal from which may exceed reference level. The video signal from the output of video amplifier 6 through the adjustable amplifier 14 and the differential amplifier 15 is fed to the first inputs of the voltage comparators 16 and 17, the second inputs of which are supplied by the reference signals UnopT and, respectively (Fig. 5). When the video signal level exceeds the reference signal levels and U (iop3 outputs of the corresponding voltage comparators 17 and 16, logical level signals are generated. The signal from the comparator 17 output goes to the first input of the OR 19 element, and the signal from the comparator 16 goes to the first input of the AND 18. Pulses from the second output of matching amplifier 2 are received at the second inputs of the elements 18 and OR 19. From the output of the element 18 and 18 the third input of the comparison unit 21 pulses are received, the number of which is equal to the number of CCD elements the video signal from which exceeds a predetermined reference level UOOPS is: (fig.5b), and from the output of element Sh1I 19, pulses are received to the third input of comparison unit 22, the number of which is equal to the number of CCD elements, the video signal from which is less than a predetermined threshold level Unop2 (FIG. 5 &.). The first input of the comparison unit 21 is given a code of a number equal to the number of picture elements, the video signal from which exceeds the reference signal level, and to the second input of the comparison unit 21 a code of a number equal to the allowable number of picture elements, the signal from which exceeds the level of the reference signal POR 3 At the first input of the comparator unit 22, a code of a number equal to the number of picture elements, the video signal from which is below the reference signal signal is fed, and a code of a number equal to the permissible number of pixels, the video signal from which is below the reference signal is fed to the second input of the comparison block signal. The operation of the device for automatically stabilizing the amplitude of the video signal can be divided into three cycles. During the first cycle, the image sensitivity of the sensor 5 on the CCD is automatically adjusted. If during the line or frame the number of pulses arriving at the third input of comparison unit 23, are longer than the numbers set on the first and second inputs of this block, then the first output at the time t (fig. 4m, period T1) is set to logical units, and at the second output at the same point in time (fig. 4n, period T1) the state of logical zero is set, at the output of the element OR 27 at time t, the state of logical zero is established (fig.4n, period T1). During the time when the frame damping pulse (Fig. AA) is equal to zero, the reversible counter 12 will work on addition and its code will increase by the number of pulses received from frequency divider 8, the accumulation time of the charge and the amplitude of the video signal will decrease (, .4p, periods T1, T2 fig.4e).

If during a line or frame the number of pulses arriving at the third input of comparison unit 23 is less than the numbers set on the first and second inputs of this block, then on its first (fig.4m, period T2) and second exit (fig.4p, the period T2) is set to a state of logical zero, at the output of the element OR 27 at the time t. the state of the logical zero is set (fig. 4n, period T2). During the time when the level of the frame extinguishing pulse is zero (fig. 4q), the reversible counter 12 will work on the subtraction and its code will decrease by the number of pulses coming from the divider time. The accumulation time of the charge and the amplitude of the video signal increase (FIG. 4p; periods of TK; T2; FIG. 4e) The accumulation time of the charge is limited to a period T (FIG. 4p).

When the maximum accumulation time T is reached, the output of the elements OR 29 (FIG. 1) will be set to a logical zero state, the output of the OR-NOT 28, OR 27 elements will be the state of the logical unit, prohibiting the counting of the reversing counter 12. The accumulation time of the video signal sensor 5 on the CCD will remain equal,

If during a line or frame the number of pulses arriving at the third input of the comparison unit 23 of the comparison is greater than the number set at the first input of the comparison block 23, but less than the number set at its second input, then at the second output of the srinene block 23 at the time point, t the state of the logical unit (FIG. 4p, the period of the TK); at the output of the OR element 27, the state of the logical unit will be established (FIG. 4n, the period of the TZ). The reversible counter 12 will not change its code, the accumulation time will not change (Fig. 4 (e), and the further operation of the automatic video amplitude stabilization device will depend on the states at the outputs of the comparator unit 22 (Fig. 1) implementing together with the logic unit 26 , a reversible counter 25, a D / A converter 31, a differential amplifier 15, a comparator of 17 voltages and an OR 19 element assigning a video signal to a level set at the second input of the voltage comparator 17.

The device for automatically stabilizing the amplitude of the video signal will begin the second cycle of operation, during which the video signal level is automatically fixed.

If the number of pulses arriving at the first input of comparison unit 22 during a row or frame is greater than the numbers recorded on the first and second inputs of comparison unit 22, then at time t, (Fig. 56), the first output of comparison unit 22 will be set to logical unit, and the second output of the comparator unit 22 (FIG. 5d), the second output of the logic unit 26 (FIG. 53) at the same time point is set to a logical zero, the reversible counter 25 will start to work on addition, increasing the binary code on its output and output potential N 31. A constant component video signal at the output of differential amplifier 15 will increase (58A period T2).

If the number of pulses received at the first input of comparator unit 22 during a row or frame is less than the numbers recorded on the first and second inputs of the comparator unit 22, then at time t, on the first (FIG. 56) and second (FIG. 5d) the outputs of the comparator unit 22 and at the second output of the logic unit 26 (Fig. 53) the states of the logical zero are established. Reversible counter 25 will work on the subtraction, reducing the binary code at its output and the potential at the output of the DAC 31.

The constant component at the output of the differential amplifier 15 decreases (Fig. 55, iriod TK),

If the number of pulses counted during a row, the frame by the counter of 32 pulses of the comparison unit 22 is greater than the number set at the first input, but less than the number set at the second input of the comparison unit 22, then at the time t, the first and second outputs of the comparison unit 22 the state of the logical unit is established (fig. 5c, d) the state of the logical unit is established and at the second output of logic unit 26 at the same time point (fig. 5 (3), the reversible counter 25 does not change its code and the further operation of the stabilization device amplitude The video signals will depend on the outputs at the outputs of the comparator unit 21, which, together with the voltage comparator 16, performs an element 18, a logical CMI unit 26, a reversible counter 24, a digital-to-analog converter 30, an adjustable amplifier 14, automatically adjusts the gain. the amplitudes of the video signal will begin the third cycle of operation, during which the span of the information signal is automatically adjusted. If the number of pulses arriving during a line or frame to the third input of the comparison unit 21 is less than the numbers recorded on the first and second inputs of the comparison block 21, then the first and second outputs of the comparison unit 21 will be set to a logical zero state. - block 26 at the time t (fig. 5e) a logical zero state is set. The reversible counter 24 during the frame damping pulse will work for subtraction, reducing the binary code at its output. The output potential of the DAC 30 will decrease. From the output of the DAC, the signal comes to the input of an adjustable amplifier 14, which will begin to increase the range of the video signal. If the number of pulses arriving during a line or frame to the third input of the comparison unit 21 is greater than the numbers recorded on the first and second inputs of the comparison block 21, then the state of the logical unit will be established at the output of the comparison unit 21, and the logical output will be set at the second output Zero, the first output of the logic unit 26 is set to zero. The reversible counter 24 during the frame damping pulse will work on addition, increasing the binary code at its output. The potential at the output of the DAC 30 will increase and the adjustable amplifier 14, controlled from the output of the DAC 30, will reduce the swing of the video signal. If the number of pulses arriving during a line or frame to the third input of comparison unit 21 is greater than the number recorded on the first input of comparison unit 21, but less than the number recorded on the second input of block 21, then the outputs of the last and first output of logic block 26 are set The TC is in the state of a logical unit, the reversible counter 24 will be stopped and the gain will not be adjusted; at the same time, the range of the video signal will be set between the levels U and (FIG. 55, period T4). When the video signal changes. At the output of sensor 5, the amplitude of the video signal is automatically stabilized during the three cycles described. Moreover, the amplitude of the video signal is more accurately stabilized by eliminating the influence of the geometric noise of the video signal sensor 5 on the CCD when generating the code received at the first inputs of blocks 21-23 comparison and also the elimination of the effect of destabilizing factors (noise, pulsed fluctuations of the video signal) during the formation of a code arriving at the second inputs of blocks 21-23 , Wherein during the first cycle of operation of the device is carried out an automatic adjustment of the video signal 5 of the sensor sensitivity of the CCD, during the second cycle occurs cutoff background component video signal during a third cycle of the information signal is controlled sweep device. Comparisons 21-23 (FIG. 2) are executed in the same way and work as follows. The pulses at the end of the line and the frame (Fig. 4b), arriving at the fifth input of the comparison blocks 21-23, at the end of the row and the frame, reset the counter 32 pulses of the comparison blocks 21-23. The pulses of the end of the frame (Fig. 4d), arriving at the quarter input of the comparison blocks 21-23, set the RS triggers 35 and 36 to the zero state. From the output of the counter 32 pulses of the comparison blocks 21-23, the binary parallel code is applied to the first inputs of the comparators 33 and 34 codes. Further operation of the comparison blocks 21-23 will be considered on the example of the operation of the comparison block 23. If during the line or frame the number of pulses arriving at the third input of block 23 is greater than the numbers set on the first and second inputs of block 23, then at the output of the code comparator 33 at time t, (fig.AI, period T1) and the output of the code comparator 34 at time tn (Fig. 4k, period T1) of block 23 of TC in pulses, at the direct output of RS flip-flop 36 at time point t (Fig. 4, period T1). and on the direct output of the RS flip-flop 35 at the time of time (Fig, AM, period T1) the states of the logical unit are established, and the output of the element I 37 at the time of time (Fig. 4n. period T1) will set the logic zero level. If during a row or frame the number of pulses, the input to the third input of block 23 (to counter 32) is greater than the number set at the first input of block 23 (at the second input of comparator 33), but less than the number set at its second input

de, (at the second input of the comparator 34), then a pulse is output at the output of the comparator 33 (fkg.2) of block 23 at time t (fig.4n, period, TZ), and there will be no pulse at the output of comparator 34 (fig, 4k, the period TK), the direct output of the RS flip-flop 36 at the time point tg (FIG. 4l, the period of the TZ) is set to the state of the logical unit, and the direct output of the RS flip-flop 35 will remain the state of a logical zero. At the output of the element And 37 at the moment of time t (fig 4p, the period of the TZ) the level of the logical unit will be established.

If during a line or frame the number of pulses arriving at the first input of comparison unit 23 is less than the numbers installed on the first and second inputs of block 23, then the output of comparators 33 and 34 (FIG. 2) | block 23 of pulses does not appear (FIG. .4н, к ,. period T2), At the outputs of the RS-flip-flops 34 and 35, a logic zero level will be set (FIG. 4 l, m, T2 period). The logic zero level will be set at the output of the And 37 element of block 23 (, T2 period) ,

koi units, and at the first output during a frame extinguishing pulse, the level is logical zero. When entering the first, second and fourth inputs of the logic unit 26 levels of the logical unit, the levels of the logical unit are established at the first and second outputs of the logic unit 26.

Thus, the presence in the video signal of the geometric noise of the video signal sensor 5 on the CCD, noise and pulsed fluctuations of the video signal does not tune the device to the level of emissions to reduce the accuracy of the device, moreover, stabilizes the amplitude of the video signal when the background illumination and spatial frequency improves transmitted image.

The clock pulse generator 1 should consist of a master oscillator and personnel shapers of the current pulse and control signals, and they can be implemented on K561 series microcircuits.

Claims (3)

The matching amplifier 2 of the output register may consist of an output control pulse generator. The operation of the comparison units 21 and 22 is identical to the operation of the unit 23. The logic unit operates as follows. Frame damping pulses arriving at the third input of logic block 26, Xi XI), endorse the operation of the block. Upon receipt at the fourth input of the logic unit 26, the signal level of the logical zero at the output of the elements IS NOT 40 and 41 ,. the first and second outputs of the logic block 26 will set the level of the logical unit, regardless of the states of the first and second input blocks of the logic block 26, when the logic unit 26 reaches the fourth input of the logical unit level, and the first input receives the logic zero level, the output of the logic block, regardless of the state, at its second input will be set the level of the logical unit, and at the second output, during the personnel extinguishing impulse, the level of the logical zero, On entering the fourth and first inputs of the logical block At 26 signals of the logic unit level, and at the second input, the logic zero level at the second output of logic unit 26, the level of the logical register and matching stages will be established. The generator of control pulses of the output register operates in the standby mode and is controlled by a clock pulse generator. Each pulse of the generator of the control pulses of the output register corresponds to the image element of the video signal sensor on the CCD. It can be performed according to the well-known scheme of the ring oscillator on the K561 LEZ chip. Claims 1. A device for automatically stabilizing the amplitude of a video signal, containing a clock pulse generator (GTI), the first, second and third outputs of which through a matching amplifiers are connected respectively by the inputs of the accumulation section, the memory section and the output register of the video signal sensor on the charge device connection (CCD), the output of which through the video amplifier is connected to the first input of the first voltage comparator, the second input of which is the input of the Topor signal, as well as the first and second elements AND, the first reversible counter, a code comparator, the second inputs of which are connected to the first outputs of the frame line length reference block, and the RS flip-flop, the output of which is connected to the control input of the sensor signal accumulator on the CCD, line end pulse generator and the frame, the first output of which is connected to the R-input of the RS-flip-flop, and the first input - with the second output of the block - counting the length of the line and the frame, the input of which is combined with the input of the frequency divider is connected to the fourth output of the GTI, different In order to increase the accuracy of stabilization, a controllable amplifier and a differential amplifier are connected in series to the output of the video amplifier; the second and third voltage comparators, the first inputs of which are combined and connected to the output of the differential amplifier, and the second inputs are inputs corresponding reference voltages, three comparison blocks, the first and second inputs of which are the inputs of the corresponding reference signals, the second and third reversible counters, logic block, three elements OR, el OR is NOT, two digital-to-analog converters (DACs), with the outputs of the first and second voltage comparators respectively through the first and second elements AND, and the output of the third voltage comparator through the first element OR are connected to the third inputs of the corresponding 6jioKOB comparison, the fourth inputs of which combined with each other and with the R-input of the RS flip-flop, and the fifth inputs are combined and connected to the second output of the end-of-line and frame pulse former, the first output of the first comparison block is connected to the inputs of the OR-NOT element and the first go reversing counter, the second input is connected to the output of the frequency splitter, the first outputs of the second and third comparison units are connected to the first inputs of the second and third reversing meters, respectively, the outputs of which through the first and second DACs are connected respectively to the control input of the adjustable amplifier and the second input of the differential amplifier , the second input of the first comparison unit is connected to the first input of the second OR element, the second outputs of the second and third comparison blocks are connected respectively to the first and second inputs of the logic unit, the third input of which is combined with the second inputs of the second OR element and the pulse generator at the end of the line and frame and connected to the fifth output of the GTI, the fourth input of the logic block is combined with the third input of the first reversible counter and connected to the output of the second OR element , the third element OR and the element OR are NOT connected in series between the outputs of the first reversible counter and the third input of the second element OR, the second inputs of the second and third reversible counters are combined m I am waiting for myself and with the second input of the first reversible counter, and the first and second outputs of the logic unit are connected to the third inputs of the second and third reversing counters, respectively, the second inputs of the first and second AND elements and the first OR element are combined and connected to the output clock of the matching output output register CCD sensor. 131 2. The device according to claim 1, wherein the comparison unit contains a pulse counter, the first and second inputs of which are the third and fifth inputs of the comparison unit, the first and second code comparators, the first inputs of which are connected to the output pulse counter, ja second inputs are the first and second inputs of the comparator, respectively, the first and second RS-flip-flops, the R-inputs of which are combined and are the fourth input of the comparator, and the output of the first RS-flip-flop is the first output of the comparator, Element And, the output of which is The second output of the comparison unit, while the outputs of the first and second code comparators are connected to the S inputs of the second and first RS flip-flops, respectively, the inverse output of the first RS flip-flop is connected to the first input of the And element, the second input 8 of which is connected to the direct output first rs-trigger 3. The device according to claim 1, wherein the logical block contains the first and second elements OR, the first inputs of which are combined and are the third input of the logic block, and the outputs are respectively the first and second outputs logical block, the first and second elements are NOT the first inputs of which are combined and are the fourth input of the logic block, the first and second elements are NOT, the inputs of which are respectively the first and second inputs of the logical block, while the outputs of the first and second elements are NOT connected to second entrance m respective first and second AND-NO elements, an output of first AND-NO element is connected to the second input of the first OR c third input of second AND-NO element whose output is connected to the second input of the second OR gate, 4