SU1252973A2 - Device for stabilizing amplitude of video signal - Google Patents

Abstract

The invention relates to television and is additional to auth.st. No. 756665. The purpose of the invention - - NIN - increase the dynamic range of the stabilization of the video signal. The device contains a generator of 1 clock pulses, a sensor 2 images on a device with charge coupling, matching amplifiers (SU) 3 and 4, SU 5 of the photosensitive section, a block of 6 samples of line and frame lengths, dividers 7 and 22 frequencies, switch 8, shaper 9 pulses end of line and frame, video amplifier 10, mismatch sensor 11, two comparators 12 and 13, D-flip-flops 14-17, elements 18-21, RS-flip-flop 23, comparator 24 codes, reversible counters (PC ) 25 and 26, register 27. Depending on whether the video signal is between the upper and lower with these values, whether it exceeds the upper value or does not exceed the specified lower value, respectively, the comparator 13 triggers, or both comparators 12 and 13, or none of the comparator 12 and 13 triggers, which is why C e (L N9 SP QD H CO N) 77

Description

The codes PC 25 and 26 remain unchanged, or the clock pulses arrive at the input of the addition or subtraction of PC 25. During the counting of the length of a line or frame, the codes of block 6 and PC 25 are compared.

one

The invention relates to television equipment, namely, devices for stabilizing the output signal of television image sensors on devices with charge-coupled communication (CCD).

The purpose of the invention is to increase the dynamic range of video stabilization.

The drawing shows an electrical structural diagram of a device for stabilizing the amplitude of a video signal.

The video signal amplitude stabilization device contains a clock pulse generator 1, an image sensor 2 on a charge-coupled device (CCD), matching amplifiers 3 and 4, a matching amplifier 5 of the photosensitive section, a block of 6 samples of the length of the frame and frame, an additional frequency divider 7, a switch 8, the shaper 9 of the pulses of the end of the line and the frame, the video amplifier 10, the error sensor 11 containing comparators 12 and 13, D-trigger 14-17, elements 18-21, frequency divider 22, RS-flip-flop 23, comparator 24 codes, reversible counters 25, additional tional down counter 26 and the register 27

The device works as follows.

If the amplitude of the video signal within a line or frame exceeds the specified value, two comparators 12 and 13 of sensor 11 are triggered, and a logical signal 1 appears at the direct output of D-flip-flop 14, and at the inverse of D-flip-flop 15 is a logical O signal. At the end of a line or frame, these signals are overwritten with And 18 and 19 elements into D-flip-flops 16 and 17. A D-flip-flop signal 1 16 prepares for

includes the voltage on the accumulation section of sensor 2. By changing the codes of PCs 25 and 26, the accumulation time is adjusted, i.e. amplitude of the video signal. A frequency divider 7, a switch 8, a register 27, and a PC 26 were introduced. 1.il.

In operation, an element AND 20 at the input of the addition of a reversible counter 25. From the moment the accumulation process begins and to its end, the third inputs of the elements 20 and 21 receive a signal 1 from the output of the RS flip-flop 23 and clock pulses from the output of the generator 1 transmitted through the first frequency divider 22 to the second inputs of the elements And

0 20 and 21. Clock pulses arrive at the input. Addition of the reversible counter 25, increasing its code by the value defined by the ratio 4N; N; K, (1)

5 where N; - the value of the current code;

iN, - is the value of the code being changed; K is the clock division division factor, K 1. When the measured code is larger than the full row or frame code (t), a reversible counter produces an overflow signal that enters the subtracting input of the reversing counter 26 and reduces its code by

25 units, and the current value of the counter 25 is zeroed out, and the clock pulse counting starts at zero. At the end of a line or frame, the pulses from the end of the formatter 9 of the implementation 9 are reset to the D-flip-flops 16 and 17 (before overwriting) and 14 and 15 (after overwriting) to the initial state, and also write the code of the reversible counter 26

35 27. According to the code value from the register, the switch 8 commits the signal of the length of the line and the frame of the corresponding frequency of the additional divider 7

40 .k fc, /.

wherefr is the line frequency

or frame;

ufpi - switching frequency;

n 1, 2, 3.

- Additional reversible counter code 26.

If the amplitude of the video signal within a line or frame does not exceed the specified lower value, no comparator 12 and 13 will work and D-triggers 14, 15 and 16, 17 will remain in their original state, while the inverse output of D-trigger 17 will have a signal logical 1, which will prepare for operation the element And 21 at the input of the subtraction of the reversible counter 25. During the accumulation time, the clock pulses from the output of the generator 1 through the frequency divider 22 begin to flow to the input of the Subtraction of the reversible counter 25, reducing its code by the value also determined from ratio (1)

When the code value is equal to or less than zero from the output O of counter 25 to the input of the addition of the reversible counter 26, a pulse enters, increasing the code by one, and the current value of the reversing counter 25 is set to the maximum value whose code corresponds to the code of the length of a line or frame. Further arrival of the clock pulses to the input. Subtracting the reversible counter 25 causes its code to decrease before the voltage supply to the CCD accumulation section is terminated.

If the amplitude of the video signal within a line or frame is within the interval between the upper and lower setpoints (deadband), then only the comparator 13 will work and, in this case, the inverse outputs of the D-triggers 15 and 17 and the direct outputs of the D-triggers 14 and 16 a logical O signal will be set, both elements 20 and 21 will remain closed and the codes of counters 25 and 26 will remain unchanged.

During the counting of the length of the line or frame, the changing code of block 6 is compared with the code of the reversible counter 25, and the code comparator 24 sets the RS flip-flop 23 to the state 1 and through the matching amplifier 5 on VNIIPI at the time of matching the codes. Order 4633/59

Random polygons pr-tie, Uzhgorod, st. Project, 4

0

0

five

c, k

K, voltage across the accumulation section of sensor 2. The voltage is removed from the accumulation section by applying a pulse at the end of a line or a frame from shaper 9 to the R input of the RS flip-flop 23. At the same time, the duration of the voltage applied to the accumulation section defined by the expression

Ti fc.kCn - K, 4N;),

where T „- the duration of the line or

frames formed by block 6;

coefficient of proportionality between code 4 Nj and the length of a line or frame. Thus, by changing the code of the reversible counter 25, the moment of applying voltage to the accumulation section of sensor 2 is regulated, and since the moment of removing this voltage is synchronized with the end of the line or frame formed by shaper 9 in frequency multiple of the line or frame frequency, changing the counter codes 25 and 26 regulates the accumulation time and, consequently, the amplitude of the video signal. Here, the dynamic range is determined from the ratio of the maximum possible accumulation time of the pulses from the output of the divider 22.

Claims (1)

Invention Formula A device for stabilizing the amplitude of a video signal according to bus No. 756665, characterized in that, in order to increase the dynamic range of stabilization of a video signal, an additional frequency divider, a switch, a register and an additional reversible counter are entered into it. moreover, the output of the block of samples of the row and frame duration is connected to the input of the end of line and frame shaper through a serially connected additional frequency divider and switch, the control input of which is connected to the output of the register, the first input of which is connected to the second output of the shaper of the end of the line and frame, and the second input is with the output of an additional reversible counter, the inputs of which are connected to the corresponding overflow outputs of the reversible counter. Irage 6J4 Subscription