SU1748283A1 - Videosignal amplitude stabilization device - Google Patents

Abstract

The use of television technology is to stabilize the amplitude of the video signal of television sensors with variable illumination. The inventive device for stabilizing the amplitude of a video signal comprises a photodiode sensor 1 of a video signal, a control unit 2, a clock generator 3, an analog processing unit 4, a peak detector 5, a switch b, an analog-to-digital converter 7, a computing unit 8, a pulse shaper 9, element 2 And 10. 1-4-5-6-7-8-10-9, 3-2. 1 tab., 7 Il.

Description

four

L 00 hO 00 s

Phie.1

The invention relates to television technology, in particular, to devices for automatically adjusting the amplitude of a video signal and can be used in digital television transmitting cameras with image sensors based on photodiode linear or non-destructive signal readout arrays.

A device for stabilizing the amplitude of a video signal is known, which contains an error sensor, an RS flip-flop, line (frame) length and exposure delay counters, as well as a number of elements and 2AND-NOT, in which the amplitude of the video signal is stabilized by decreasing or increasing the number of clock pulses input to the exposure delay counter at the time of accumulation. However, such a device does not provide a high rate of stabilization of the amplitude of a video signal with significant differences in illumination and at the initial time after switching on the device. The decrease in the stabilization rate in the first case occurs due to the fact that the magnitude of the change in the accumulation time is chosen proportional to the accumulation time itself, rather than the magnitude of the change in input light, which caused the existing change in the video signal. In the second case, the phasing of the exposure delay counter relative to the row length counter is uncertain, which may require a greater number of stabilization steps.

Closest to the invention is a video amplitude stabilization device comprising an image sensor on a charge coupled device (CCD) in which the signal is not stored after reading, a control unit controlled by a single vibrator, a series-connected video amplifier, a peak detector with a reset, a subtraction unit with a reference voltage source; an analog-to-digital converter (ADC) and a computing unit. At the end of each read interval, this device, using the measured maximum signal and known accumulation time, calculates and sets the value of the optimal accumulation time at which the maximum signal level will be near the Optimal level U0, irrespective of the change in the input illumination level. This method of regulation can significantly improve the speed of the device, but with a sudden change in illumination or at the beginning of operation of the device it needs to perform at least two cycles of signal accumulation (one to determine the maximum illumination, the other to register the signal), which leads to loss of

registered information.

The aim of the invention is to improve the accuracy of stabilization with sudden changes in illumination.

The goal is achieved by the fact that

0 to a video amplitude stabilization device containing a series-connected photodiode sensor and an analog processing unit, a peak detector, an analog-to-digital converter, a block

5, the control unit and the computing unit, the first output of which is the output of the video signal amplitude stabilization device, are introduced a switch, the first and second information inputs of which are connected to

0 outputs of the analog processing unit and the peak detector, respectively, and the output is connected to the information input of the analog-digital converter, the output of which is connected to the information input

5, the computational unit 2I, the first input of which is connected to the second output of the computational unit, the pulse shaper, the first, second, third and fourth inputs of which are connected respectively to the third and fourth outputs of the computational unit with the output of element 2I and the first output of the control unit, and the output is connected to the reset input of the peak detector, as well as the clock generator, the input

5 of which is connected to the first input of the control unit and to the fifth output of the computing unit, and the output is connected to the second input of the control unit, the third input of which is connected to the sixth

0 by the output of the computing unit and with the second input of the element 2I, the fourth input of the control unit is connected to the output of the pulse shaper and to the first control input of the computing unit, and

5, the first, second, third, fourth, and fifth outputs are connected respectively to the first and second inputs of the photodiode video signal sensor, to the control input of the analog processing unit, to the clock

0 analog-to-digital converter input, with the combined control input of the switch and the second control input of the computing unit, the third control input of which is connected to the output of the analog-digital converter. In electronics, functional elements entered into the video signal amplitude stabilizer circuit are known. However, the presence of new connections between them made it possible for the proposed device to select the optimal accumulation time in one cycle of signal accumulation with a sharp change in the input illumination or at the beginning of the device operation. This quality is not the result of the summation of the positive effects achieved from the introduction of new Elements or the use of ready-made technical solutions is achieved precisely by the presence of new connections between the elements.

1 shows a functional diagram of a device for stabilizing the amplitude of a video signal; Fig. 2 is a schematic of an elementary cell of a photodiode image sensor, allowing non-destructive readout; FIGS. 3 and 4 show possible functional diagrams of a polling unit for a linear and matrix photodiode receiver; FIG. 5 shows a possible practical implementation of a computing device; FIG. figure 6 - the algorithm of the computer computing device; Fig. 7 shows timing diagrams explaining the operation of the video signal amplitude stabilization device.

The proposed stabilization device includes a photodiode image sensor 1, a control unit 2, a controlled clock generator 3, an analog processing unit 4, a peak detector with a reset 5, a switch b, an analog-to-digital converter (ADC) 7, a computing device 8, a read start pulse generator 9 and element 2И 10 In this case, the polling outputs 12 of the control unit 2 are connected to the same output terminals of the image sensor 1. The output of the image sensor 1 is connected via an analog processing unit 4 to the input of a peak detector with a reset 5 and the second input of the switch 6, the first input of which is connected to the input of the peak detector with reset 5, and the output through the ADC 7 is connected to the information inputs 19 of the computing device 8. The first and second clock outputs 13 and 14 of the control unit 2 are connected respectively to the clock input of the unit analog processing 4 and with the start input of the ADC 7. The read end output 15 of the same block is connected to the second synchronization input of the computing device 8 and the control input of the switch 6.

The output of the conversion end of the ADC 7 is connected to the first synchronization input 20 of the computing device 8. The information outputs 21 and the write output 22 of the computing device 8 are connected to the same inputs of the read start pulse generator 9, the control output 24 is connected to the same inputs of the controlled clock generator 3 and control unit 2, the first start output 23 is connected to the first input of element 2 and 10, the second start output 25 is connected to 5 the second input of the same element and through the control unit 2 is connected to the erase output and an image sensor 11 1.

The clock input of the read start pulse generator 9 is connected to the third to 0 clock output of the control unit 2, the start input is connected to the output of the 2I 10 element, and the output is connected to the clock input 16 of the control unit 3, the reset input of the peak detector 5 and to the third input

5 synchronization of the computing device 8,

As a photodiode image sensor 1, designed to convert radiation into electrical

0 signal, you can use, for example, a photodiode array LF-1024 or a photodiode array (FDM) MF-14, the photodiode cell FDI 1 shown in figure 2 includes the photodiode itself

5 26, the erase transistor 27, the amplifying transistor 28 and the switching transistor 29.

The pins of the anodes of all the photodiodes of the cells are combined and connected to the common pin

0 power source. The drains of all erase transistors are also combined and connected to the output of the bias source. The information signal is removed from the source of the amplifying transistor 28 when

5 is applied to the gate and to the source of the switching transistor 29 of a positive voltage. In the matrix FDI, the origins of the switching transistors are combined and connected to the polling pins, and their

0 gates are connected to the paging columns. In linear FDIs, the gates of these transistors are connected to the outputs of the digital shift register, and a constant voltage is applied to the sources.

5 The possibility of non-destructive readout is provided by the high input resistance of the amplifying transistor 28. To erase the accumulated signal, the gate of the erasing transistor 27 is supplied

0 high voltage level

The control unit 2 provides for the reading of the signal from the elements of the FDI 1 by generating pulsed control voltages in accordance with the organization

5 of this image sensor. This unit can be made on the basis of the widely used 155, 176 series microcircuits according to the functional diagram; shown in FIG. 3 for linear FDIs; in FIG. 4, for matrix ones. In FIG. 3, the counter 30 together with the decoder 31 generates the phase pulses of the interrogation 12, as well as the clock pulses at the first and second clock outputs 13, 14. The counter 32 and the trigger 33 form a positive read out pulse at the output 15 with a duration equal to the phase pulse polling.

4, the role of the counter 34 and the decoder 35 is similar to the role of these elements in the circuit of FIG. Registers 36 and 37 are used to generate polling signals in rows and columns of a matrix FDI. Trigger 38 serves to generate a read end pulse at output 15. Trigger 39 synchronizes the operation of registers 36 and 37 with the arrival of a signal from the output of the read start pulse generator 9. Possible element the base of the polling units: counters 30, 32 and 34 - K155IE7, decoders 31 and 35 - K155REZ, triggers 33, 38 and 39 - K155TM2, registers 36 and 37 - K155IR1.

A pulse generator connected to output 18 via a multiplexer can be used as a controlled clock generator 3, the generator being connected to one of the multiplexer inputs directly and to the other through a pulse divider. The control input of the multiplexer is connected to the control input 24 of a controlled clock generator 3. The element base of the generator 3: pulse generator - K531GG1, pulse divider - K155IE7, multiplexer - K155KP2,

The analog processing unit serves to amplify the signal and prepare it for conversion to a digital sample. For this, unit 4 must contain an amplifier with a sample-hold circuit.

Serial ADCs of type F7077 / 1 or F4223 with the number of bits of 10-12 and a conversion time of 5-10 µs, having a start input and a conversion end output, can be used as an ADC 7 in the device.

The computing device 8 serves to control the clock generator 3 and the shaper of the start of reading pulse 9, synchronize the accumulation processes and read the signal in the image sensor 1, calculate the optimal and additional accumulation time, record the maximum and current samples of the image sensor 1. One of the practical implementation options of the computing device 8 on the basis of a computer with a common highway (channel) of type Electronics-60, Electronics MS 1201.01 is shown in FIG.

The computing device 8 includes both standard blocks, a processor, a random access memory and a permanent storage device (RAM and ROM), and

an original interface unit containing a bus transceiver 40, control decoders 41 and 42, control status register 43, a decoder 44, triggers 45, 46 and 48, a HE element 47, a transmitter

0 49, elements OR 50 and 54, element AND 51, address counter 52, random access memory 53 and data register 55, ROM is intended for storing the work program and constants, RAM is for storing

5 current variables. Under the control of the processor, the program reads from the ROM and executes it. At the same time, the data, the address control signals are transmitted between the units via a computer channel.

0 A bus transceiver 40 is used to match the computer channel with the elements of the interface unit, the outputs of which are connected to the information inputs of the decoders 41 and 42 of the control signals,

The 5 inputs of the state register 43 are the information outputs of the computing device 8. The pulsed control signals from the output of the decoder 41, generated by the auxiliary signal TO OU, are used to record information into the elements of the interface unit, and similar signals from the output of the decoder 42 serve for reading information and transmitting it to a computer channel. So,

5, in particular, the signal h is used to write codes to the state register 43, signal 2 resets the address counter 52, signal 3 is transmitted to the output of record 22 and accompanies the transfer of information to the outputs 21. Signal 14 supplied to the input of the receiver 49, is produced entering information about the state of the trigger 48, the signal Is is used to read information from the RAM 53, the signal 1e reads the maximum signal from the output of the register 55 in the computer.

The state register 43 together with the decoder 44 and the triggers 45, 46 and 48

0 are used to synchronize the process of reading the signal from the image sensor 1 and the process of writing the corresponding digital samples to the RAM 53. Thus, the trigger 45 controls the passage of pulses from the first

5 synchronization inputs 20 through an IL-I element, 50 to the recording and sampling inputs of RAM 53. Trigger 46 generates a signal at the output of control 24. Trigger 48 generates a ready signal indicating the end of the reading interval of the signal from image sensor 1, a set of codes which are recorded in state register 43 and form control signals are given in the table.

The OR elements 50 and 54 allow the passage of actively low signals from the first synchronization input 20 to the input of the RAM 53 record and to the clock input of the register 55 when the second inputs of these elements are supplied with control voltage of a low level, When these inputs are fed to control inputs high level transmissions of actively low signals to the output of these elements are blocked. Thus, with respect to actively low signals, these elements work as AND elements (negative logic) and allow controlling the passage of pulse signals.

The RAM 53 serves to store the samples of the image sensor signal 1. The capacity of the RAM 53 is equal to the number of elements of the image sensor 1, and the size of the ADC sensor 7. The RAM 53 has recording and sampling inputs, and the samples are recorded at the same time low level, and readout when a low level signal is applied to the sample input. In the remaining cases, the RAM 53 is in the storage mode, and its outputs are in the third state.

The third state register 55 is used to store the maximum sample signal of image sensor 1 and, like RAM 53, has recording and sampling inputs. A sample is recorded at a low signal level at the write input, and it is read at a low signal level at the sample input. Transmitter 49 also has a third output state and is controlled by a low level signal.

Element base of computing device 8 is possible: processor - MS1201.2 with built-in ROM, bus transceiver 40 - 589PP26, decoders 41, 42 - 155ID4 (inputs V - 2, 14. In the decoder 42 inputs 2, 14 are grounded), register 43 - 155ТМ8, triggers 45, 46, 48 - 155ТМ2, counter 52 - 155IE7, RAM 53-537RUZ, register 55 - 531И Р22, transmitter-155LP8.

The read start pulse shaper 9 can be executed on the basis of a programmable interval timer chip (for example, KP580, VI53) having information inputs (D), recording input (W), start input (G), clock input (C) and output (O), the Timer is programmed to operate in the hardware triggering mode of the pulse and generates a pulse at the output with a delay of N clock pulses. Regarding the start time, where N is the number,

pre-recorded timer information inputs using the recording signal.

Element 2 and 10, in accordance with the state table of elements And for actively high input voltages, generates a high output voltage when there is a high voltage at both inputs. Thus, the occurrence of a low voltage level at any of the inputs leads to the appearance of a low voltage level at the output of this element.

Thus, the device for stabilizing the amplitude of the video signal can be made on the basis of elements that are produced in the form of ready-made microcircuits or are formed from them using standard circuit solutions.

The device as follows.

When the device is turned on or when the input luminance changes abruptly, the computing device 8 (Fig. 1) should switch the controlled clock generator 3 to form higher frequency pulses, initiate signal accumulation in the image sensor 1 and count the minimum accumulation time Tn min-in the read start pulse shaper 9. At the same time, after the interval Tn min expires, the shaper 9 resets the peak detector 5 and initiates the reading of the image sensor 1 signal by the control unit 2 At the end of the interval, Vani SDTV min computing device 8 by a signal from the control unit 2 must switch controlled by a clock generator 3 to work in the nominal mode. At the same time, the switch b connects the output of the peak detector 5 to the input of the A / D converter 7, which is started by the control unit 2. After the conversion is completed, the maximum signal of the image sensor 1 from the output of the A / D converter 7 must be written to the computing device 8, which is based on linear signal and luminance of the image sensor 1

UM Em Tn, (1)

calculates the maximum illumination of the em (in relative units) and the value of the optimal accumulation time Tno, at which the maximum value of the signal will be in the vicinity of the optimal level U0

Eat

Um1

,

but

Th.min Up Up

Eat um1

Tn

min

(2) (3)

On the basis of the calculation of the TNO and the data on the current accumulation time of the signal Tn., The computing device 8 should calculate the time interval DTNo required to increase the maximum signal of image sensor 1 to the level

U0

 DTno Tno-Tn.t, (4)

enter the corresponding number in the read start pulse shaper 9 and start it again via element 2 and 10.

At the beginning of the re-reading of the signal of the image sensor 1 after the DTT time interval relative to the time Tn.t, the total accumulation time of the signal will be equal to Tno and in accordance with expression (3) while Em is constant during the accumulation interval of illumination

Km Em Tno Uo, (5)

those. the amplitude of the maximum FDI 1 signal when re-reading will be stabilized at the optimal level Do for one accumulation interval regardless of the maximum luminance of the Em. The set of samples of the image sensor signal 1 with the maximum amplitude thus stabilized from the output of the computing device 8 is transmitted to the stabilizer device.

To perform these functions, units of the device for stabilizing the amplitude of a video signal, taking into account their practical implementation, should work as follows.

When the device is turned on or when the input light changes abruptly, the computing device 8 (Fig. 1) with a high signal at the control output 24 switches the controlled clock generator 3 to the operation mode with an increased pulse frequency. At the same time, at the polling outputs 12 and at the clock outputs 13 and 17 of the control unit 2, pulses with an increased frequency are also generated. The formation of clock pulses at output 14 in the presence of a high level signal at control input 24 is blocked (Fig. 3 and 4) and ADC 7 does not start.

To switch the clock generator 3 on the control input 24, the computing device 8 uses a trigger 46 (Fig. 5), which is set to one state by the decoder 44 by transmitting code 3 to the status register 43. The code is transmitted from the computer ROM of the computing device 8 via a bus transceiver 40. Similarly, by transmitting codes 1, 2, the triggers 45 and 46 are set to one, and the high level of the signal from the direct output of the trigger 45 blocks the passage of low-level pulses from the first sync input. tions 20 through the element 2 or 50.

To initiate signal accumulation in

The image sensor 1, the computing device 8 (Fig. 1), by the information outputs 21, using the write signal at the output 22, enters into the pulse shaper the read start 9 the value of the minimum accumulation time

m T.min / -h

Mt.minu, (o)

where Ti is the period of the pulses of the generator 3 at

operation with an increased frequency, and generates a start pulse at the output 25. The recording signal at the output 22 is formed by the decoder 41 (FIG. 5), the start pulse at the output 25 is formed by the decoder 44

when writing to the state register 43 of code 5. A start pulse from output 25 passes through the control unit 2 to the input 11 erasing the image sensor 11 (figure 1) and in each cell of this sensor (figure 2) opens

erase transistors and bias photodiodes 26 in the opposite direction to the ECM. At the same time, the same pulse passing through element 2 and 10 starts the read start pulse shaper 9, which, in accordance with the previously entered number at an interval of time Tn min, generates a pulse at the output 16 (Fig. 7). This pulse resets the peak detector 5 and is initiated

reading the image sensor signal 1 by generating the corresponding polling pulses at the outputs 12 of the control unit 2 (FIGS. 3 and 4). At the end of the read interval Tcch.min (Fig. 7), peak detector 5 records the maximum value UM1 of the image sensor signal 1.

Upon completion of the read interval, the control unit 2 at output 15 generates a read end pulse (Fig. 7),

which connects the output of the switch 6 and, therefore, the input of the ADC 7 to the output of the peak detector 5, and triggers the trigger 46 of the computing device 8 to the zero state

(Fig, 5). The low level of the signal at the output of the control 24 of the computing device 8 switches the controlled clock generator 3 to the generation of clock pulses with a nominal frequency and enables

generation of clock pulses at output 14 of control unit 2. During the action of the pulse of the end of reading, a clock pulse from output 14 of control unit 2 starts ADC 7 and the maximum signal is transmitted from its output to information inputs 19 of computing device 8 together with the signal of conversion end, incoming at the first sync input 20 of the same device. The input of the low level signal to the input of element 2ILI 54 from input 20, while simultaneously submitting to the second input of this element, a low level reading signal from the output of inverter 47 results in the appearance of a low level signal at the output of element 2IL or 54 and the record of the maximum signal reading in register 55 The writing of subsequent samples of the signal to the register 55 is blocked by applying a high level signal to the second input of element 2 OR 54 after the completion of the read end pulse at the second synchronization input 15. The falling edge of the pulse ends The readout 15c of the output of the inverter 47 trigger 48 switches to the zero state, and sets a high signal at the input of the receiver 49 The appearance of the high signal at the input of this receiver indicating that the maximum signal of the image sensor 1 has been written to the register 55 8 by polling the receiver with the signal Сам. The self-counting of the maximum signal UM1 is inputted into the computer of the computing device 8 with the aid of the signal b supplied to the sample input of the register 55. After entering the countdown cial trigger signal 48 is set to the initial state of the transmission code 2 in the Status Register 43

Based on the data on the maximum signal UM1 and the time of its accumulation, Tn min of the computer of the computing device 8 calculates the value of the optimal accumulation time Tn by the formula (3) and the value of the ATNo accumulation time increment required to increase the maximum image sensor 1 signal by the formula (4) to the optimal level Uo. After completing the calculations, the computing device 8 enters into the pulse shaper the read start 9 the value of the additional accumulation time

%

ATN T2

(7)

where Ta is the period of the clock pulses of the generator 3 in the nominal mode, and starts the driver 9 with the pulse at the output 23 passing through the element 2 and 10 (Fig.7). The formation of a pulse at the output 23 in the computing device 8

(FIG. 5) is performed by transferring code 4 to state register 43

By the time the trigger starts, the read start pulse 9, i.e. to the moment

the starting point of the interval DTNO, the current accumulation time Tnt signal in the image sensor 1 will be equal to the sum of the intervals Tn min, Tsch min and Trasch, where Trasch time input into the computer of the computing device 8

0 of the maximum counting signal UM1, calculating M, 1T, recording the magnitude of the additional accumulation time and triggering the read start generator, 9 The magnitude of the Trasch is constant for a specific

5 of the implementation of the stabilization device and can be determined by the NC based on the passport data of the blocks included in it or experimentally. The value of TSh min is determined by the maximum reading frequency.

0 image sensor signal 1. The magnitude Tn min is chosen from the condition UM Do when Em Emmax, Tn-Th min min, where EMax is the maximum possible illumination Besides, when Em Emmax, in order not to

5 to allow signal saturation when it is accumulated, it is necessary to monitor the observance of the following relationship between temporal and amplitude parameters

Uo

Tn

(eight)

Ub Tn min N Tsch min b b Trasch where UB is the upper level of the input voltage of the ADC 7.

Modifier inequality (8), we get

Tn min-g -.- .. (Tssh min Trasch). (9) UB - Uo

At the beginning of re-reading the signal of the image sensor 1 through the interval

time ATNO relative to the moment of TNT, the total accumulation time of the signal will be equal to Tno and in accordance with the expression (3) with a constant Em

im-tno i0, (10)

those. the amplitude of the maximum signal of the image sensor 1 when re-reading will be stabilized at the optimal level Uo regardless of the magnitude of the maximum illumination Em.

The input of the signal samples with the amplitude thus stabilized in the computer of the computing device 8 is performed as follows.

55 To initiate the input process in the computing device 8 (Fig. 5) by the signal 2, the counter 52 is set to the zero state and at the information input of the trigger 45 by transmitting the code O to the register 43

the state sets a low voltage level. When a trigger for a read start from the third synchronization input 16 of a computing device 8 arrives at the clock input of this trigger, it switches to the zero state and lows the signal from the direct output and allows the pulse of the conversion end to pass from the first synchronization input 20 through element 2IL 50 to the RAM recording input 53 and further through the element 2 and 51 to the input sample of the same RAM (Fig.7). Simultaneous delivery of low-level signals to the control inputs results in writing to the RAM 53 samples of the signal from the information inputs 19 of the computing device 8. By the falling edge of the sampling pulse, after the end of the recording, the address generated by the counter 52 is automatically increased by one,

 At the end of the interval of the falling edge of the end of the pulse input from the second synchronization input 15 through the element NOT 47 to the clock input of the trigger 48, the latter switches to the zero state and sets a high signal level at the input of the transmitter 49. After detecting the high level signal the input of this transmitter by cyclic polling by the signal M of the computer of the computing device 8 by transmitting code 1 to the state register 43, the trigger 45 is set to one and the high level of the signal from it The direct output is blocked from passing low-level signals to the write input and sampling of the RAM 53. The process of recording the signal samples in the RAM 53 is completed.

The reading and reading of the maximum signal samples from register 55 is performed in this way. At this stage of the stabilization device operation, the maximum signal value read from register 55 is used to control the accuracy of the stabilization. So, when finding the maximum signal UM in the tolerance zone U0 - A.DUp UM U0 - AiDomp the computer of the computing device 8 reads the signal samples from the RAM 53 and transfers them to the output of the computing device, for example, to the screen of the graphic display or to the central computer . Otherwise, the computer generates a stabilization error message, which can be associated, for example, with a malfunction of the elements of the stabilization device or with an unforeseen change in the maximum illumination during the signal accumulation interval.

The information is read from the RAM 53 into the operative memory of the computer of the computing device 8 by means of the pulse Is after the counter 52 is reset to the initial state by the signal 2,

To implement the described mode of operation of the device for stabilizing the amplitude of the video signal after it is turned off or when the computer light changes dramatically

computing device 8 should work in accordance with the algorithm shown in Fig.6. The program that implements this algorithm can be placed in the permanent memory of the computing computer.

devices 8 together with the parameters Tn.min, TSCH min, Trasch, TL T2, U0, DUdop, which are previously determined experimentally or by calculation.

Thus, the introduction of the photodiode image sensor 1 into the composition of the device being offered allows one to carry out a non-destructive signal reading in the process of its accumulation and to obtain information on the magnitude of the maximum

FDI 1 signal, and therefore, the maximum illumination of this sensor. The non-destructive readout of the signal in FDI 1 allows its accumulation to continue after the reading and to exclude

Thus, the loss of time to re-accumulate the signal in similar receivers with destructive readout. The introduction of the switch 6 allows you to measure the amplitude of the maximum signal

FDI 1 by connecting the output of the pmkovy detector 5 to the input of the A / D converter 7 with a minimum delay after the end of reading the signal of this sensor, the introduction of a controlled clock generator 3 makes it possible to accelerate the reading of the signal at the stage of the initial assessment of maximum illumination and reduce, therefore, the time interval obtaining such an assessment.

Turning on the read start pulse shaper 9 allows forming intervals of a minimum Tn min and additional accumulation time and, finally, the introduction of element 2I 10 allows starting the read start pulse shaper 9 as simultaneously with the start of signal accumulation in the FDI 1 when the Tn.min signal is generated, and in the process of accumulation during the formation of the interval LTO.

The introduction of these elements into the device for stabilizing the amplitude of the video signal allows for the accumulation of the signal of the FDI 1 during the interval Tn min.

its subsequent non-destructive reading with a maximum speed during the TSH min and measuring the maximum amplitude of UMI, estimate the maximum illumination by Em using the formula (), calculate the optimal accumulation time Tno using formula (3) and the additional AT accumulation time interval form the ATNO interval and read the FDI 1 signal after the end of this interval. Since the TNT value was calculated from the condition of finding the maximum FDI 1 signal in the vicinity of the optimal level U0, it amplitude will be stabilized at this level irrespective oturovn maximum illumination within one integration interval, i.e. as fast as possible

Claims (1)

Invention Formula A video amplitude stabilization device containing a series-connected photodiode video signal sensor and an analog processing unit, a peak detector, an analog-to-digital converter, a control unit and a computing unit, the first output of which is an output of a video amplitude stabilization device that in order to improve the accuracy of stabilization during abrupt changes in illumination, a switch was introduced, the first and second information inputs of which are connected to the outputs of the analog block brabotki and peak detector sootvetst- Code value Allowing the recording of signal samples in RAM 53 Disabling the recording of signal samples in RAM 53 Resetting the ready trigger 49 Setting the control signal generation trigger 46 Signal conditioning at the first launch output 23 Formation of a signal at the second launch output 25 Standby state (used to generate pulse signals when applying codes) and the output is connected to the information input of the analog-digital conversion, the output of which is connected to the information input of the computing unit, the element I, the first output of which is connected to the second output of the computing unit pulse generator, the first second, third and fourth inputs of which are connected respectively to the third and the fourth output of the computational unit with the output of the element I and the first output of the control unit, and the output connected to the reset input of the peak detector, as well as the clock generator, the control input Which is connected to the first input of the control unit and to the fifth output of the computing unit, and the output is connected to the second input of the control unit, the third input of which is connected to the Sixth output of the computing unit and to the second input of the And element, the fourth input is connected to the output of the pulse shaper, and the first control input of the computing unit, and the first, second, third, fourth, and fifth outputs are connected respectively to the first and second inputs of the photodiode video signal sensor, to the control input of the analog processing unit openings, with a clock input of an analog-digital converter and with a combined control input, a switch and a second control input of a computing unit, the third control input of which is connected to the output of the conversion end of an analog-digital converter v Perform function + fcM S.t / Ј4 / t / frf about FIG. 2 + Ј FIG. four t 20 i ROM Ram K8Y8 n to input, 4-1 1h L Phage. $ 4-2 36 2Z J ( Start Give codes, Z, G6 register 43 ± Record the number of NT. min shaper 9 ± Pass a CoU To Register 43 DSG Get ifMJ number from ff Calculate the optimal cumulative burden of Tio accumulation and time increments dTno ± Burn uislo & ngyo shaper ff i Send code% 0 about register 45. Reset counter 52. Flag  the readiness (reception m1K.43) is established Yes Accept UM number from register 85 {end,) FIG. 6 not