SU1515168A1 - Computer to user interface - Google Patents

Abstract

The invention relates to computing and is intended for interfacing software-controlled external devices with a computer. THE PURPOSE OF THE INVENTION IS THE EXTENSION OF THE FUNCTIONAL OPPORTUNITIES OF THE DEVICE BY ACCESSING THE POSSIBILITY OF CONNECTING TO A Subscriber's Computer With A Non-Standard Interface. The device comprises an address receiver unit 1, address decoder 2, control signal decoder 3, address transmitter block 4, transceiver block 5, data transmitter block 6, second receiver block 7, status register block 8, third receiver block 9, processing block 10 interrupt, first receiver block 11, first, second, third, fourth transmitters 12,13,14,15, interrupt vector transmitting unit 16, fifth transmitter 17. The device provides reception and transmission of information to the subscriber on the initiative of both the computer and the subscriber / by interrupt. 1 il.

Description

one

(21) 4362845 / 24-24

(22) 01/12/88

(46) 10/15/89. Bul No. 38 (72) V.I. Razlom, B.I.Brovko, V.V. Belogub and V.V. Zaichenko (53) 681.3 (088.8)

(56) USSR Copyright Certificate 1156652, cl. G 06 F 13/00, 1985.

Device matching unit УСТ-60-02.

(54) DEVICE FOR COMMUNICATING COMPUTER WITH SUBSCRIBER

(57) The invention relates to computing and is intended for interfacing software-controlled external devices with a computer. The aim of the invention is to expand the functionality of the device by providing the ability to connect to the subscriber computer with a non-standard interface. The device contains

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address receiver block 1, address decoder 2, control decoder 3, control address block 4, transceiver block 5, data transmitter block 6, second receiver block 7, state register block 8, third receiver block 9, interrupt processing unit 10 first block

The invention relates to computing and is intended for interfacing software-controlled external devices with a computer.

The aim of the invention is to expand the functionality of the device by providing the ability to connect to the subscriber computer with a non-standard interface.

The drawing shows a block diagram of the proposed device. The device contains an address receiver unit 1, an address decoder 2, control signal decoder 3, an address transmitter block 4, a transceiver block 5, a data transmitter block 6, a second receiver block 7, a status register block 8, a third receiver block 9, processing block 10 the first unit, the first receiver unit 11, the first, second, third, and fourth transmitters 12, 13, 14, and 15, the interrupt vector transmitting unit 16, the fifth transmitter 17.

The interface operates as follows.

A device may request program interruption on two separate interrupt vectors A and B.

Vector A is established by the signal TR A N, and vector B - by the signal TR B B N, received from the subscriber with a small amount of appropriate permissions.

The exchange of information between the computer and the subscriber is carried out by means of pro - gram operations with flag polling or program operations using the means of program interruption.

For device addressing, the last 4K address space of the computer is used.

The addresses are transmitted to the subscriber (signals A 01-09, 11 H) when the computer is accessing the interface device at specific addresses.

11 receivers, first, second, third, quarter transmitters 12, 13, 14, 13, interrupt vector transmission block 16, fifth transmitter 17. The device provides reception and transmission of information to the subscriber on the initiative of both the computer and the subscriber (on interruption). 1 il.

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The device contains in block 8 status registers, two addressable status registers PCO and PC2.

The RSO status register has three bits. The PCO5 bit is used to enable or disable the transmission of the address to the subscriber. When writing to this bit 1, the transmission of the address to the subscriber is permitted. A bit can only be recorded by a computer.

The PCO 06 bit (permission bit B B) can be read and written by a computer and serves to control the logic of the device.

The PCO 15 bit (TP-B request signal) can only be read by software. It is set by the subscriber and is used as an interrupt request signal. It is usually generated by the corresponding trigger of the subscriber, which is established when service is required.

The PC2 status register has two bits. The PC2 06 bit (resolution signal A and B) can be both read and written by the software and serves to control the logic of the device.

The PC2 07 bit (TP A B request signal) can only be read by software. This bit is set in the same way as the PCO 15 bit.

The presence of two signal requirements, TP A B and TP B B, allows for more flexible programming. Usually, one of the requirements is used to indicate that subscriber data is ready for input into a computer, and the other, that the subscriber is ready to receive information.

The device is capable of transmitting information to the subscriber from the computer in sixteen bit words that are not stored in the device itself. When the subscriber is contacted, the address and the address synchronization signal are set. And with the delay required for decipher 15

Address radios by the subscriber, data is set that is received by the subscriber.

The device is capable of receiving information from the subscriber and transmitting it to the computer in sixteen bit words without intermediate storage.

The computer, when accessing the subscriber from which it expects to receive information, sets the address of the subscriber who receives this address when there is a synchronization signal and sets the data to the output of block 7. With the delay required to set the data, the data is transmitted to the output of block 5 and received in the computer.

When operating the device with a computer, the following main operating modes are possible: recording information in the PCO or PC2 status registers; reading information from the PCO or PC2 status registers; information output from the computer to the subscriber, input information in the computer from the subscriber; generating signals for interrupting programs for subscriber service.

Consider the operation of the device in each of the listed modes.

Record information in the state registers RSO or PC2.

The computer exposes to the data bus (to the input of block 5) information (signal K DOO-15 N) for writing to the status registers, to the input of block 1 - the address of one of the device status registers (signals K ADROO-17 N) to the first and the second inputs of block 11 are the operation code (signals K V / VO, K V / V1 N, respectively). Data from the computer through the block 5 is fed to the inputs of block 8 (signals DOS B and D06 B). Then, after a certain time required to compensate for the mismatch of the transmitted signals and to decipher the address in the device, the computer transmits to the second input of unit 1 a synchronization signal K CA N;

Signals K ADROO-17 N and K CA N come in block t of the address receivers, from the output of which the decoder 2 addresses receive signals SA L ADR 17 V, ADR 15 L 16 V, ADR 14 L 13 B, ADROO-12 V. Decryptor 2 decrypts the received address. When the address received from the computer coincides with the address of the status registers, the decoder 2 generates a UV B signal and a PCO B CHOICE signal when accessing the state register

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PCO or PC 2 V SELECT signal when accessing the PC 2 status register.

The generated signals PICB SELECT 5 P1I PIC2 PICT B decoder 2 addresses are fed to the decoder 3 control signals, which also receives B / V B and V / V 1 B signals from the block 11 receivers. In accordance with -composition of the input signals, the decoder 3 generates signals: SP B and one of the signals of the VOUOD PCO.V or OUTPUT PC2 B. The development of these signals is possible TCknbKo in the presence of a signal

15 HC B from the output of the decoder 2. By the signal EXT RSO V or OUTPUT PC2 V, entering block 8, bits D05, D06 or DOB are recorded in the bits of the status registers, respectively, which are received from the computer through the block 5 transceivers. According to these signals, block 8 generates a signal PCO 05 B and the permission signals RAZ A B (PC2 06 V) and RAZ B B V (PCO 06 V). The synchronization signal of the SP B is generated by the decoder 3 with the delay necessary to receive information in the status registers.

The first transmitter 12 on signal

0 synchronization 1 and SP B generates a channel synchronization signal of the passive device K SP N, which enters the computer. The computer, having received the signal K SP FI, removes the signal K CA N from the second input of block 1, and then the data from the input of block 5 and the operation code from the inputs of block 11. After removing the signal KSA H, the decoder 2 address is removed in the interface device

0, the signal is HC B and the operation of the decoder 3 control signals is prohibited. The removal of the shock signal B causes the removal of the signal K SPN from the output of the first transmitter 12, which indicates the computer to complete the output operation. This completes the cycle of exchange with the computer.

Read the information from the POS and PC2 status registers.

The readout of the registers of the state of the RSO (bit PCO 06, PCO 15) and PC2 (bit PC2 06, PC2 07) are performed as follows.

The computer sets the input to unit 1

the address of one of the device status registers (signal KADROO-17 N) and to the inputs of block 11 is the operation code (signals K V / VN, K V / V1 N, respectively).

Then, with the delay required to compensate for the error of the signals and decipher the address in the device, the computer places the synchronization signal KA H on the second input of block 1. The state registers are decrypted by dep1 the address 2 in the same way as described in the recording mode information in the status registers.

In accordance with the combination of input signals, if the HC signal is present, the decoder 3 generates one of the signals of the INR RSO V or INPUT PC2 V signals and with the delay necessary for establishing information on the computer data outputs, the synchronization signal SP V. The INR signal RSD B enters the transmitter 13 and transmitter 15, allowing the front of 15 12 V, and in block A of the address transmitters, signals ADROO-11 V are received. If the address of the subscriber received from the computer is included in the group of selected addresses from the address space of the computer, the bits of the RSOOBIRSO 15 transmitters are 20 encoder 2 formir The HC signal, which enters Block 4, allows the subsequent generation of the subscriber's synchronization signal SA H, as well as to the decoder 3. In accordance with the combination of the input signals. The decoder 3 generates the following control signals: FORMER V, STROB ADR B CAt Н, СП V. On a signal OUTPUT In block 6 data transmitters places data

(figure 1). After the data is set, the transmit 30 (DOO-15 N signals) to the data bus Ab13 and 15 form the channel data signals and expose the channel signals TO DOB N and K D 15 N, respectively. The ENTER signal PC2 B enters transmitters 13 and 14, allowing transmission of bits PC2 06 and PC2 07. Similarly, the transmitters 13 and 14 form the channel data signals and expose the signals TO DOB N and K D07 N, respectively

The sensor 12 sets the synchronization signal K SP N. The computer, having received the signal K SP N, reads the data from the outputs of the transmitters 13-15 and removes the signal K CA N from the second input of block 1, as well as the signals of the operation code.

By removing the signal CAB Hb, the interface signal is removed by the decoder 2 and the signal UV B is generated and the operation of the decoder 3 of the control channels is prohibited. The removal of the signal from the UV B causes the removal of the signal K to CPN, which indicates the computer to complete the operation of entering information into the computer. At this exchange with the computer is completed.

Information output from the computer to the subscriber.

Information output from the computer to the subscriber is carried out through the block 5 of transceivers and the block 6 of data transmitters as follows.

The computer exposes the transmitted data (signals K DAOO-15 N) to the input of block 5 and the address of the subscriber (signals K ADROO-17 N) to the first input of block 1. In addition, to the inputs of block 11, the computer sets an operation code to output information ( signals К В / ВО And, К В / В1 Н, respectively). Data from the computer through

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nta. The VGOOD B signal is generated with a delay necessary to establish data at the outputs of a block of 6 data transmitters, taking into account possible mismatches.

With a delay relative to the signal O output H, the decoder 3 generates the signal CA1 B, which enters unit 4 of the address transmitters, the STROB ADR B signal also arrives there. On the STROB ADR B signal, 4 sets the address of the subscriber (signals A01-09, 11 N) to the address bus of the subscriber, and the generation of the CA H signal, which is generated by the CA1 B signal, is also permitted.

Thus, the subscriber receives the data, the address, and with a delay to compensate for the error and the synchronization signal SA N.

With the delay required to receive information by the subscriber, the decoder 3 generates a signal SP B. The first transmitter 12, using the signal B, generates a synchronization signal K SP H, which is fed to the computer. Having received the signal K SP N, the computer removes the signal K CA N, and then the data and the code of the operator 1.ShI. After removing the signal K CA N in

Block 5 is fed to the inputs of a block of 6 data editors.

Then with the delay required

to compensate for the mismatch of the transmitted signals and decrypt the address in the computer device, it places the synchronization signal of the active device K CA N to the second input of block 1.

Signals K ADR 00-17 N and K CA N come to block 1 of the address receivers, from whose outputs to the decoder 2 of the address signals SA L ADR 17 V, ADR15 L 16 V, ADR14. L 13 V, ALROO- are received.

12V, and ADROO-11V signals come to the A block of the address transmitters. If the subscriber’s address received from the computer is included in the group of selected addresses from the address space of the computer, the decoder 2 generates an HC signal B which enters into block 4, allowing the subsequent generation of the synchronization signal of the subscriber SA N, as well as to the decoder 3. In accordance with the combination of the input signals, the decoder 3 generates the following control signals: EXIT V, STROB ADR V CAt N, SP V. The OUTPUT B signal in block 6 of data transmitters puts data

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nta. The VGOOD B signal is generated with a delay necessary to establish data at the outputs of a block of 6 data transmitters, taking into account possible mismatches.

With a delay relative to the signal O output H, the decoder 3 generates the signal CA1 B, which enters unit 4 of the address transmitters, the STROB ADR B signal also arrives there. On the STROB ADR B signal, 4 sets the address of the subscriber (signals A01-09, 11 N) to the address bus of the subscriber, and the generation of the CA H signal, which is generated by the CA1 B signal, is also permitted.

Thus, the subscriber receives the data, the address, and with a delay to compensate for the error and the synchronization signal SA N.

With the delay required to receive information by the subscriber, the decoder 3 generates a signal SP B. The first transmitter 12, using the signal B, generates a synchronization signal K SP H, which is fed to the computer. Having received the signal K SP N, the computer removes the signal K CA N, and then the data and the code of the operator 1.ShI. After removing the signal K CA N in

the signal is removed from the interface device, and the operation of the decoder 3 is prohibited. The removal of the signal from the signal B is caused. The removal of the signal K SP N, which indicates the computer to complete the operation of outputting information to the subscriber.

Entering information into the computer from the subscriber

The input of information into the computer from the subscriber is carried out through the receiver unit 7 and the transceiver unit 5 as follows.

After receiving the subscriber's address from the computer and when the data entry operation, the decoder 3 generates (according to 06 and РСО 06), independently of the combination with the input sig-friend, allow or prohibit the transfer of the following control signals: giving the appropriate requirements to the computer ENTER , STROB ADR B, SPV, CA1 B. Post-interruptions from the subscriber.

If the subscriber receives addresses by signals CA1 B, ADB STROPS B, the subscriber exposes the data to the input of block 7, which through him enters the inputs of block 5. With the delay necessary to compensate for the error of the data signals from the subscriber at the inputs of block 5, the decoder 3 sets in block 5 an INPUT signal N. According to this signal, the data is placed on the output. After installing the data transmitter 12 out-. It turns off the synchronization signal K SP N. The computer, having received the signal K SP N, reads the data from the data bus and removes the signals K CA H and the operation code. By removing the signal CA N in the interface device, the generation of a signal of the air-boring device is stopped and the decoder is prohibited.

3 control signals. The data is removed from the bus 18. The removal of the HC signal causes a removal of the signal K SPN, which indicates the computer to complete the operation of entering information into the computer. : In this, the data entry cycle in the computer from the subscriber is completed.

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In response to the appearance of the ZKCH N channel backup signal at the output of the 10 E unit, it exposes the signal to the PKU B to the input of the 10 unit. When it appears, the device takes the pairing / lock signal of the K NFC N channel, forms and before the output of the 10 the response signal confirming the choice of K P N, when KOTOpoi is implemented, the computer removes the channel signal K PKC V.

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blocking calls to the subscriber, both during the withdrawal and when entering information. This is necessary when the subscriber performs a continuous process. To do this, the PCO 05 state register is written in the preceding operation O, which prohibits the generation of the STROB ADR B signal by the decoder 3. In this case, the transfer of the address of the vector signals AO1-09,11 N and the signal CA N |

are not generated until -5 pin of computer data. the call barring will not be lifted (1 will be recorded in the RSO 05 bit) or the subscriber will not request service (TRA N, TRB N signals).

After the end of the cycle, the channel is connected to the channel and the K KZ signal is produced, the interface device generates the signals of VEK B and K PI.

Signal VEK B comes from the block to the fifth channel transmitter 17

The address of the interrupt vector can be incremented along the K D02 N bus through the CENTURY CENTURY B C signal.

Generating program interrupt signals to serve the subscriber.

The interface device contains interrupt logic compatible with the computer channel, which allows the subscriber to generate interrupt requirements.

With the help of two independent signals TRA N and TRB N, arriving at the inputs of block 9, the subscriber can request an interruption of the computer program at two separate interrupt vectors. In addition, two bits of the status register are TIMES A C and TIMES B C (bits

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The presence of interrupt requirements can be determined by a computer by the state of signals K D0.7 N or K D15 N ...

Since each interrupt requirement has its own vector, one of the requirements can be used to indicate that the subscriber data is ready for input into the computer. Another interruption requirement may be used to indicate that the subscriber is ready to receive new information.

The channel signal of the channel request K SSCH N is generated when the enable triggers of the block 8 of the status registers are set and the corresponding request is interrupted from the subscriber.

In response to the appearance of the request signal of the SCCH channel N at the output of the computer unit 10, it puts a signal K of the CCCH B at the input of the block 10. When it appears, the interface device removes the channel C request signal of the SCRC N, generates and transmits: from the block output 10 a response signal confirming the selection of K P N, when a KOTOpoi appears, the computer removes the channel signal K PKCh V.

does not allow the transmission of the address of the | interruption from the output of block 16 to

allows the transmission of the address of the | interruption vector from the output of block 16 to

After completion of the cycle of connection to the channel and generation of the К КЗ Н signal, the interface device produces the signals ВЕК and К ПРР N.

Signal VEK B comes from block 10 to the fifth channel transmitter 17 and

pin computer data.

The address of the interrupt vector can be incremented along the K K D02 N bus according to the signal from CENTURE B B. If an interruption occurs from the TRB signal H sig} gal VEK B

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has a high level, and when a QT signal interrupt occurs, the TPA H signal is low.

The addresses of the interrupt vectors are as follows: interrupt by the TRA H signal; interruption by signal N. N.

Thus, the address of the vector of the vector is interrupted on the computer data bus and a signal K PRR N is formed, at the same time the device resets the signal K PV N and transmits a signal to the input К К К N.

The computer receives a signal K PRR N, waits 75 NS to compensate for the variation in

the arrival time of the address of the vector preggeani, takes the address of the interrupt vector (signals K D02, 03, 05 N) from the data bus and transmits the synchronization signal K SPN N.

The interface device receives the signal К СП Н and removes the signal of the CRCD, the address of the pre-Grigani vector, the signal К КЗ Н, i.e. A computer channel transmission is active.

The computer resets the signal K SP.N, having collected the reset signal K PRR N, and enters the interrupt sequence to memorize the current contents of the CS comacd counter and the status register of the RSP processor and replace them with the abort vector of this device .

Claims (1)

Invention Formula A device for interfacing a computer with a subscriber, comprising a transceiver unit, first, second, third receiver units, first to fifth transmitters, interrupt processing unit, address decoder, data transmitters unit, address transmitters unit, control decoder signals, the state register I block, the block of the transmission of the vector of the break, the input-output device for connecting the computer data bus is connected with the input-output of the transceiver unit, respectively, with the first, second The inputs to the device for connecting the first to third outputs of the computer mode are the first to the third inputs of the first receiver block, the outputs of the first to fourth transmitters are the outputs of the device for connecting the synchronization input and the first to third inputs of the computer, respectively. p that 55 the synchronization inputs of the status register block, the fourth output of the control signal decoder connected to the first information input of the second transmitter, the fifth output of the control signal decoder connected to the second information input of the second transmitter, the sixth, seventh output of the control signal decoder eight 12 the transmitter is a group of outputs of the device for connecting a group of computer data inputs, the input of the second receiver unit and the output of the data transmitter unit are the input-output device for connecting the subscriber data bus, the output of the address transmitter block is the output of devices for connecting to the subscriber address bus, the first the second entrances of the third Q 15 20 five 0 five 0 five the receiver unit are the device inputs for connecting the subscriber intercept request signal outputs, the output of the second receiver unit is connected to the information input of the transceiver unit, the output group of which is connected to the input group of the data transmitter unit, the output of the sixth and sixth bits of the output unit group of transceiver units correspondingly with the first, second information inputs of the state registers unit, the first output of which is connected to the first resolution inputs of the second transmitter and the interrupt processing, the second output of the status register block is connected to the second resolution inputs of the second transmitter and the interrupt handling block, the third output of the status register block is connected to the first input of the control signal decoder, the first output of the third receiver block is connected to the second input of the control signal decoder , the information input of the third transmitter and the first input of the interrupt processing unit interrupt, the second output of the third receiver block is connected to the third input of the decoder control of their signals, with the fourth informational input of the transmitter and the second input unit prershani prershany processing the first output of decoder control signals coupled to the invariant: formation input of the first transmitter, the second, third outputs of the decoder control signals connecting 5 the synchronization inputs of the state register block, the fourth output of the control signal decoder is connected to the first information input of the second transmitter, the fifth output of the control signal decoder is connected to the second information input of the second transmitter, the sixth, seventh outputs of the control decoder signal are connected to the resolution inputs of the corresponding block transceivers and a block of data transmitters, the first, second outputs of the first block of receivers are connected respectively to the fourth, fifth inputs of the cipher from the first to the outputs of the address decoder are connected, respectively, from the sixth to the eighth inputs of the decoder of the control signals, the outputs of the first and second signals of the interrupt processing unit vector, respectively, to the first, second permission ports of the fifth transmitter, group information inputs of which are connected to a group of outputs of the interrupt vector transmission block, the third output of the first receiver block is connected to the reset input of the state registers block, characterized in that enhancement of the device functionality by providing a computer with a nonstandard interface, a block of address receivers is entered into it, the information input and synchronization input of which are the device inputs for connecting the address bus and the output of computer synchronization respectively, the output of the address receiver block is connected with the first information input of the block of address transmitters and with the input of the address decoder, the third output of which is connected to the input of times, the address of the block of transmitters of the address, per the second, the second outputs of which are the outputs ycTj) oAcTBa for connecting the address bus and the subscriber synchronization input, the eighth, ninth outputs of the decoder control signal, are connected respectively to the synchronization input and the second to third outputs of the address transmitter unit interrupts are the outputs of the device for connecting, respectively, the request inputs, sample confirmation and interrupt resolution, the fourth output of the interrupt handling unit is connected to the output of the devices for connecting a computer synchronization input, the fifth, sixth inputs prershany processing unit are input devices for respectively connecting channel capture outputs and providing a computer channel, fourth, fifth vkody decoder control signals are connected respectively to the data inputs of the fourth and third transmitters.