SU648974A1 - Interface - Google Patents

Description

(54) DEVICE FOR PAIRING

HdiR informational outputs of the device, the output of the register of the state and the first output of the data register are connected to the corresponding: the output outputs of the main doors ({the main output of the device, the second input and output of the data register are connected to the corresponding inputs and outputs of the main output in the spy inputs and outputs of the device, the third input the data register and the second input of the cipher block of commands are associated with the group of information inputs of the device; the second output of the state synchronization block is connected to the fourth input of the data register, the second inputs are register and addresses and register states and entry to the third decryption unit commands t23,

However, this device has a low speed, since the search for a request for a connection is realized by following the leg of the olros of the states of all the functional modules of the district-wide system.

The whole invention is to improve the speed of the device.

This is achieved due to the fact that the exchange control block, the bind encoder, connected to the first output - the input block of the communication request address generation unit, are entered into the device, the second, third and fourth inputs of which are connected respectively to the device information inputs; synchronization in the output of the address decryption block, the information inputs of the state atator are connected to the second input at the Output of the data register, and the control vmdium input is connected to the second output of the synchronous and the first About the exchange control block, the first exit of which is connected to the fifth inlet of the synchronization block, the output of the communication request addressing flea is connected to the address output of the device; two call outputs and the answer input of which are respectively connected to the second and third outputs and the second input exchange control unit.

FIG. 1. pre-jalana block diagram of the device; FIGS. 2, 3, and 4 show the time diagrams of information exchange between the common bus interface (processor) and the inter-block autterface of the peripheral system.

The block diagram of the device contains a block I deia (} address address, block 2 interrupt, register 3 data, register 4

addresses, block 5 command codes, re. rist 6 states, block 7 synchronous price, encoder 8 states, block 9 to form the address of communication requests {ES}, block 10 control exchange, second Group and informational inputs and outputs 11 devices, group output addresses 12 devices, rpytma command outputs 13 devices, output 14 Call 1 (B1), output 15 Call 2 (B2) devices, input 16 of the device response; a group of inputs 17 states of the device, an input 18 of the request for communication of the device.

Unit 1 selects the addressable registers (3, 4, 6 or 5) of the device registers, and also the decryption of control signals (write, read). Block 2 organizes the capture of a common bus in order to interrupt the processor. The data register 3 buffers the data transferred between the processor and the functional modules.

Address register 4 stores the address of the function module that is being accessed. Block 5 receives from the processor the codes of program signals that instruct the addressed functional module to execute those OR other actions (input, output, reset, start, analysis of ES, etc.). The state register 6 records the state of the inter-block interface (busy, free), the state of the addressed functional module, the mask, etc. Block 7 performs a general synchronization of the device operation in accordance with the control signals of the OR and the signals of the inter-block interface . The encoder 8 converts the positional code (during the search for CS) into the binary code of the ES address. Block 9 provides a multi-level search for ES and the subsequent storage of a | juded aaf) eca ES. Block 1O organizes the management of asynchronous data exchange over the interconnect interface.

The device provides software data exchange between the process {registers 3, 4, 6 and unit 5 of the device.

Claims (2)

The presence in the device of the encoder 8 states and blocks 9, 1 O of the device allows the device to exchange data with peripheral functional blocks and search for 3aiqxxx B communication (formation of the address of the ES) in the autonomous mode. The device works as follows. The processor communicates with the device at the level of the device registers, and the data transfer between the device and peripheral blocks and the search for communication requests is performed without the participation of the processor. Registers 3, 4, 6 and block 5 are accessible by the processor and the latter can be set to them in the write and read modes in accordance with the program interface. The processor registers to the device registers for the following purposes: sending to register 3 or reading data from register 3; sending to register 4 the address of the fschshionalny modul to which it is required to make a call for input or output of the terminal; sending in block 5 signals, writing. to the addressed functional module, some actions (input, output, start, reset, etc.), reading the status code for register 6, as well as setting the masks in register 6. The procedure for transferring data from the proxy to the functional module is In the following, the processor sends data to register 3, addresses to register 4 and the program code corresponding to the drive mode to block 5. After VTO, the processor shuts down and the device autonomously organizes a communication cycle with the addressed module via the inter-block interface. sponds to the diagram shown in FIG. 2. At the beginning of the peak, the second group of information inputs - outputs II from register 3 is given a data, the address address group 12 from register 4 has the value of the address of access and the command output group 13 is the pickup of the command code. After a fixed delay Tl of the time necessary for the address to be recognized by the functional module, unit 10 is started and, at output 14, it sets the signal B1. The addressed functional unit (alement), by signal B1, starts a prescribed operation (in the pressure case, the reception of danviohs from the second group of internal form and II inputs) and, after its execution, notifies the device of this response signal From input 16. By means of the signal From unit Yu, after time outputs output 15 to signal B 2, which is relayed in the function block, as received from the signal. Block 1O after the disappearance of the response signal. From does the shutter speed TC, then resets the signal B1 and notifies the block 7 about the state of the communication session. 7, after a delay of the TC., Generates a control signal, using which information, address and command signals are disconnected, as well as a B2 signal from the interface trunk. This completes the procedure for transferring data from the processor to the function block. The transfer of data from the footscore modules to the pre-sand control is as follows. The processor sends the address to the address, the rotation, and in the block, 5, the command code corresponding to the output mode. Further, the device dried the communication loop with the functional module (see FIG. 3). Block 7 organizes the connection of address signals from register 4 to rpytmy address outputs 12 and signals from block 5 to a group of command outputs 13. After time T, block 10 is started and output 14 sets the call for command B1. The addressable function module in the B1 output mode on the B1 generates information signals to the input from the group of information inputs and outputs 11. The status signals to inputs 17 and notify the device with a response sigma From. The signal from block 1O produces a signal b 2, which leads to a reset of the signal from. Then, over time, the device receives data from the inputs and outputs 11 into register 3 and the status signals into register 6, after which communication with the functional module is disconnected — signals from outputs 12, 13 and 15 are reset. can produce in the program exchange mode on interrupt. The device provides an automatic (without the processor) parallel analysis of communication requests and the formation of the AP address in three levels: the formation of the address of the functional unit (AFB); the formation of the address of the functional element (AFE), us76 tanryvnogo in the block; Formulation and / res channel (AK) in a functionaldong;;: - ..;: in eite. The address word and this service is the following format of AFB AFE And in 7 4-3О Functional unit (FB), epeme-yy (PV) or a channel requiring a non-service request, sets up a cirrHan 3G in input 18 of the interconnect-about interface ,, This sieves signal is from block 5 of the code 7, which issues control signals to blocks 5 and 9 1 ph5: block 9 is set to the initial state (AFB 0, AFE O, AK O), and U block 5 generates the command code g; ;;. and Ali ZS. Then block 7 performs the following command: sending the command code to exit 13 –i address signals from block 9 on. &Amp; - -. moves 12 inter-unit interfaces (4; ig., 4) At AFB O, the code of the command of the paragpel analysis of the ES will be exalted:; emf; a1Ktsiokalshimi block1 1 and (.prn all addressing is done to the address) After a fixed delay T: i; on r. t-code - the call signal E1, On signal-out;:; B1 function blocks are installed. On the corresponding information: the corresponding lines, the signals are state,; indicating your presence (or absence of information; block, as a function of the functional blocks of the signal transmission signal. sostopikl to ttrkses clear to him the information {io: -: to carry out operations on B1) yda-dat, drove the answer from one way to another, with his speed performance of the glp-H; /; b- :: kov answer sigils are output to input K not simultaneously, but with scattering (f ™) n, therefore, the reception of the ustgox-progla state does not occur according to the tk coe: the cho. ka all of the FBs do not complete the above-mentioned HERO operations until the B1 signal does not STRICT response signals from. To ensure automatic hooking for speed, -t-hz-.rіnykh fushshyonalny blocks block device 10 of the device, receiving a response signal from the fastest FB. the output of the signal B 2 to output 15 is perceived by the entire f5T1Cnational blockkvmn and is relayed by them to input 16 in accordance with time 1, i.e. Signals from and B2 vgts -:,: G; -and; O1g -; cl;: Ochigo5) ib, k ,. In this way,.: C;: op: an1: “of those who completed their years; atoms. Oper Ny on signal B1 and: iM; - raS; -: vin- Egna-gg From before the second type of B2, the lastnap produces the sigiapa From ,, In bposy of not completed observations of the operations of B1 (respectively. Cor. 58Ts-BUT not billed ;, response) signbl B 2 retraksliruyutt; to input 16 Q signal part From the answer. Then, in the fuction blocks, the end of the EB5 Popnzni B1 operations results in the resetting of the signal from the response of the retransmission of the BGNAP B 2. Consequently, with a parallel analysis of the Loss signal from the ROSOV by the leverage of the signal From: .-: B1: ode 18 indicates that most bystrodeistBuy fuyus c; :: april block aacoachil execution :: / - er 7ti- “GSiVBny B1 {i.e. issued ss: 5: 11 :: eEP1L about the presence of CS i-Hi C1 from 5 of a third of 1s1 s Information). Removing the signal from the bus 16 herEkterizuev: onchiii perform performance on the BJ in the very slow fuk: n; ionally l (pokoy By removing the link from b ok 7.n ppevvifi T; .g (ft; g. 4) implements subg ; 1; o - ;: the group of the iforg..aicon inputs: p.m. to 11 from gpjfraa-oru 8 which: rogrodnto kodnrzvakieg EattrnLer Xb- and developed by a single piping paganeno ko za, ib. LETTER Code ad ad Cii FB-v.shche.ashego ZS, Encryptor 8 is equipped with the following system: - 1n. H code address AFV YAS with stfratora 8 zag; remove: s block 9 "After that, the block l. About pierce. do reset B. I. and after THz the jS unit 7 resets the signals to the instruments; ocet: 12, 13 and IS; :; sopMtjpo.BaHS5o address of the functional blot, requiring a request for a link to the list of peripheral blocs ;;; 5 address kotkh) ry already defined. For WTO, block 7 organizes the issue of block 5 of the command code corresponding to the local distribution system, which is 13 n In block 9, to outputs 12 of the address of the control panel as AFB G1, AFE O, AK O. o in the VTO case, the address of the IPMF for addressing all functional elements in the addressed FB (), Communication with functional elements and the formation of the address of an AFE functional element that has set the AP signal is described in a similar way. At the end of the communication cycle, the AFB function block addresses the address funkts AFE P1, if the functional elements in the peripheral block are multichannel, the cycle of forming the channel address AK p arranged the signal of the CS after the formation of the full CS address (, AK p) the block 7 issues a signal to the block 2 interrupts, on which the latter performs the general bus operation to capture the OSH and interrupt the processor. Upon entering the interrupt, the processor accesses the block and reads the complete address of the communication request. Thus, the device allows parallel analysis of communication requests with asynchronous group processing of response signals applied to one bus. This makes it possible to significantly reduce the processor response time to communication requests and adjust to the maximum speed of the peripheral blocks. Claim device containing interface decryption unit connected by inputs to corresponding inputs from grunt control device inputs, interrupt unit connected two-way communication with address decryption unit, output of which is connected to first commands of data register, register, command encryption unit , the state register and the synchronization unit, the first output of which is connected to the first input of the interrupt unit connected by the second input to the corresponding input from the group of control inputs of the device The group of outputs of the interrupt block is connected to the corresponding control outputs of the device, the second inputs of the data register, the address register, the status register and the command encryption block are connected to the second BbJXonoM of the syn- 741 O po: .ization, the second and third inputs of which are connected with the state input to the device communication request input, the output of the command encryption unit is connected to the third input of the synchronization unit to the command output of the device, the first and second outputs of the address register are connected respectively to the address group The device's common outputs and a group of informational outputs of the device, the output of the status register and the first output of the data register are connected to the corresponding outputs from the group of information outputs of the device, the second input and output of the data register are connected to the corresponding inputs and outputs from the group of information inputs and outputs of the device , the third input of the data register and the second input of the command configuration block are connected to the group of information inputs of the device, the second output of the synchronization block is connected to the fourth input of the reg the data source, to the second inputs of the address register and the state register, and to the third input of the command encryption unit, characterized in that, in order to improve speed. devices, an exchange control block, a state encoder connected by an output to a first input of a communication lock address generation unit, the second, third and fourth inputs of which are connected respectively to a group of information inputs of the device, a second output of a synchronization block and an output of an address decryption block, the information inputs of the state encoder are connected to the second input to the RegSpra Data Output, and the control input is connected to the second output of the synchronization unit and the first input of the exchange control unit , the first output of which is connected to the fifth input of the synchronization unit, the output of the addressing unit of the communication request address is connected to the address output of the device, the call output terminal and the answer input of which are respectively connected to the third output and the second input of the exchange control unit. Information informatics accepted in the field of expertise l.Iiatamation, 1976, №e, рр89-92. 2. Guide to the subsystem IPS11, Eynard, MaccaHyce-i-c, USA, mprpt 1972. Vcfpoijcmfo fft / L7A / gA Rig.Z iPut.fycmuffi c i. ffi / ffVfrrr nod either. f S