SU1695312A1 - Device for interfacing channel of input-output with subscriber - Google Patents

Abstract

The invention relates to digital computing and can be used in computing systems for interfacing external devices with an input / output channel of a digital computer. The purpose of the invention is to increase the speed and reduce the cost of equipment of the device. The goal is achieved by introducing an address multiplexer, command execution control unit, operating mode storage node, information decryption node, command issuing node, and a command multiplexer into the device containing a communication unit with a channel, a rep unit, information meshes, a data multiplexer and a buffer memory. addresses, instruction decryption node and communication trigger node with subscriber. 9 il.

Description

&

AND

The invention relates to digital computing and can be used in computing systems for interfacing external devices with an input / output channel of a digital computer.

The purpose of the invention is to increase the speed of the device, reducing equipment costs.

v Figure 1 shows the block diagram of the device; FIGS. 2-6 are diagrams of command issuing and address nodes, information decryption, a communication trigger node with a subscriber, command execution control node, operating mode storage node: FIGS. 7, 8, 9 show Record, Read Modified Command Algorithms , Input Output .

The device (Fig. 1) contains the information register unit 1, the communication unit 2 with the channel, the command execution control unit 3, the data multiplexer 4, the buffer memory (PSU) 5, the operating mode storage node 6, the address multiplexer 7, the decryption node 8 information, node 9 decryption instructions, node 10 issuing commands and addresses node 11 trigger communication with the subscriber, a group of clock inputs 12.

Node 10 issuing commands and addresses (Fig. 2) contains the switch 13, the circuit 14 priority, the trigger 15 (Call), the register 16 commands, the register 17 addresses, the multiplexer 18, the decoder 19.

Node 8 decryption of information (Fig 3) contains from the first to the seventh elements 20-26 And, the first element OR 27, the eighth element And 28, triggers 29 and 30 Read / Write and Attribute, trigger 31 Start gender, trigger 32 Begin formation of command O SL CO

YU

nor, trigger 33 Start of formation of indication 1, trigger 34 Resolution, second element OR 35, from ninth to eleventh elements 36-38 I.

The node 11 of the trigger for communication with the subscriber (FIG. 4) contains the trigger 39 bytes of the ATSD 2000 state (BS-A), the trigger 40 bytes of the updated state of the ATSD 2000, the first and second elements I 41-42, the trigger 43 of the CCT-1, Trigger 44 SI-VI, First Element OR 45, Third Element And 46, Trigger 47 Call, Trigger 48 Issue Command, Trigger 49 SI-B Record, Trigger 50 SI-B Read, Trigger 51 Write, Fourth Element And 52, First Element AND-OR 53, trigger 54 OBR, fifth and sixth elements AND 55.56, second to fourth elements OR 57-59.

The node 6 modes of operation (figure 5) contains the first element AND 60, trigger 61 Continue, trigger 62 Sign of loading, second to fifth elements AND 63-66, register 67 modes, first element OR 68, trigger 69 Search, register 70 Note, from the sixth to the ninth elements AND 71-74, the second element OR 75, from the tenth to the thirteenth elements AND 76-79, the first element AND-OR 80, the counter 81, the second element OR 82, the fourteenth and fifteenth elements AND 84-84.

The command execution control node 3 (FIG. 6) contains the first to the fourth elements AND 85-88, the counter 89, the trigger 90 data bytes, the first element AND-OR 91, from the fifth to the eighth element AND 92-95, the second element AND -OR 96, trigger 97 End of channel exchange, trigger 98 Select crystal, trigger 99 Read, trigger 100 Write, ninth to thirteenth elements AND 101-103, trigger 104 data preparation, from the twelfth to fourteenth elements And 105-107, first through fourth elements OR 108-111, trigger 112 chains of commands, the fifteenth element AND 113, the fifth element OR 114, with six of them the ninth to the nineteenth element AND 115-118, the third element AND-OR 119, from the twentieth to the twelve sixth element And 120-126, the fourth element AND-OR 127, the sixth element ILSE 128, the twenty-seventh element And 129, the seventh and eighth elements OR 130-131.

Fig. 1 shows lines 132-152 of internal links.

Unit 1 is used to store state information, to generate and output information to the channel, to decipher command codes executed by the device, to store information about the types of errors. Block 2 serves to organize the exchange with the channel. Node 3 provides performance

commands in accordance with its algorithm and the current state of the BSD, and also sets the mode of the device operation, controls the mode of operation of the PSU, sets the byte pointers of the QC state, VUK. Multiplexer 4 organizes the transfer of information between the nodes of the device. Buffer memory 5 is designed to store the current ATSD 2000, as well as for BS and BUGS

0 eight ATSD 2000. Node 6 storage modes

jobs meant to sync

device node interactions. The device operates in the following modes: reception

information from the channel in BP5; issuing information from BP 5 to the channel; input information from ATSD; information output on ATSD; processing information in the device. Multiplexer 7 is designed to store and set the current BP5 address, as well as to form

0 addresses of the service area. Node 8 is designed to generate pointers in the event that modified fields, field attributes, or null information are found in BP5. Node 9 decryption

5 instructions is designed to decrypt the instructions coming from the channel and ATSD. Node 10 issuing commands and addresses designed to form a command and address issued in the ATSD, Node 11 communication triggers

0 with the subscriber is designed to implement a temporary interaction between the device and the ATSD 2000.

The device works as follows.

5 The device is intended for input and output of information on an alphanumeric display. The device provides input from an external device (WU) information to the buffer memory (PSU), conversion and

0 transfer of information to the computer input-output channel, as well as displaying the information received from the computer input-output channel on the screen of a VU.

The structural scheme of a realizable device consists of two complete parts of the interconnection, interconnected by means of a unified communication interface. The first part includes mating with input-output interface 0 blocks 1, 2, which ensure the execution of channel sequences. The structure of the second part of the device includes interface with the WU interface - nodes 10, 11, control nodes 3, 6, 8 and processing 4, 5, 7,

5 9 information.

In blocks 1, 2, channel sequences are performed: initial sampling signals of data transmission signals entered by a subscriber, operation completion signals, the result of each

Sequences are internal interface signals that activate at node 3,6, 10 the appropriate circuits for executing the current command.

The principles of command execution and interrelation between device nodes can be shown to the greatest extent by the example of command execution Record, received from a computer I / O channel. In the initial sampling sequence, block 2 generates a signal for successful completion of the initial sampling, which is transmitted via bus 146 to nodes 6 and 10 and sets the trigger 62 Boot symptom if buffer memory 5 is loaded with information from the slave. In this case, block 1, receiving a command from the I / O channel, writes it to the command register, decrypts it, and generates on the bus 142 to execute the signal of the current command from the channel 3 (the Write command). The Zan signal arriving via the bus 142 is required to process requests only from the addressed WU, whose address was issued by the channel on the Record command. If the sign of loading of buffer memory 5 is not set, then memory 5 is loaded with information from the slave unit. The loading is carried out with the help of node 6, which sets (for nodes 10 and 11) on bus 133 a mode Entering information from the slave. Nodes 10,11 are means of interface of the device under consideration with the VU interface - T. In this device, these nodes execute the necessary commands to receive and send information to the alphanumeric display, and also provide transmission to the interruption channel with the status byte. . The loading of the buffer memory 5 with information from the screen of the alphanumeric display is carried out according to the algorithm shown in Fig. 7. The loading procedure is carried out by executing a sequence of four commands on the -T interface: Read manual entry, Retrieve status, Enter, Retrieve status. On the Read manual entry command, the service information from the OS is read, in which the marker location code on the alphanumeric display screen and the code of the pressed function key on the alphanumeric display keyboard are transmitted. On the Enter command, the memory 5 is loaded with information located on the screen of the slave. The command Output state checks the result of the command Read manual entry and Input. The node 11 (FIG. 4) provides the generation of control signals for recording the received information in block 5.

Upon completion of receiving information from the HEU, node 3 generates a PSU Load Signal, which indicates that the memory 5 has been successfully loaded and the device is ready for further execution of the current command. The node b removes the Input mode and sets on the bus 133 the Receive data mode from the computer channel to the power supply unit. In this mode, data is transmitted, which

0 is determined by block 2, where a data byte signal is generated that provides for writing or reading information from the memory depending on the current channel command being executed. The session 5 communication with the channel is controlled through block 2 by setting in node 3 a data preparation trigger 104, which is established when the device is ready to receive or transmit data.

0 The algorithm for processing incoming information is shown in Fig.8. After control of the node 3 will receive information and determine the completion of the reception, node 3 generates a pointer

5 bytes of the device state The channel has terminated, which indicates that the device has completed its operation in the Receive data from channel to BP mode, the node 6 has removed this mode of operation, and in block 2 it has

0 transmission to the channel of the device status byte. After this, the mode Information output from the memory is established through nodes 10. 11 via the interface - T in the slave. The procedure for issuing information of the buffer memory 5 is implemented under the control of node 11, which provides the generation of control signals for issuing information from memory 5 to the slave unit.

After transferring the entire array of information from the buffer memory 5 to node 11, the output sequence is completed by receiving the state-end state byte from the VU. Then a state byte pointer is formed.

5, when transmitted to a channel in order to indicate that the command specified by the channel has been executed. During the execution of the Write Node 3 command, it detects possible errors and sets appropriate

0 instructions in the byte of the updated device status.

The initial stage of the execution of the Read Modified command is similar to the execution in the Write command. but

5 after the loading indication is removed and the Input mode is removed, the node 6 sets the mode Output to the computer information from the buffer memory 5. In this mode, it is possible to view the contents of memory 5 and output it to the channel in block multiplex mode. The issuance algorithm is shown in Fig.9. After the output of the information from the buffer memory 5 to the channel is completed by the Stop signal coming from the channel or after reaching the memory limit 5, node 3 completes the Read Modified command by issuing device state bytes to the channel Finished channel, V. U finished.

The device also performs a number of other commands in the computer channel: Erase the record, Erase all unprotected, Read, the execution of the listed commands is based on the above algorithms.

The nodes of the device are as follows.

The command execution control unit 3 (FIG. 6) generates signals that ensure that each node performs the corresponding actions. The node 3 serves to control the communication between the computer channel and the slave. Node 3 supports device operation in accordance with the requirements of the I / O interface and the requirements of the interface - T,

During the execution of the Input mode, node 3 ensures the sequential recording of information into memory 5. After the information is fixed at node 11, node 3 sets up a trigger 98 Select a chip and a trigger 100 Record, which on the bus 141 form signals Setting Address BP, Account Address BP. These signals allow you to record the incoming byte of information from the slave at the corresponding memory address 5. In the mode of receiving information from the channel, a data byte is sent via bus 142 and a trigger 90 is set at node 3, followed by 90 data bytes and 100 records the incoming byte of information from the channel into memory 5 at the current address stored in node 7. Counter 89 counts the incoming signals of the data byte and, since the device operates in block-multiplex mode, after receiving the eight and bytes of information, the data preparation trigger 104 is reset and the mode of receiving data from the channel is cleared. After node 3 is ready to receive the information byte again, a trigger 104 is set to receive the next block of information from the computer channel. 2, via bus 142, generates a Stop signal, through which a trigger 97 is set at node 3. The end of the exchange with the channel and a signal is formed on bus 143 to form a status byte with a pointer. In the output mode, in node 3 sequential installation of triggers 93 and 99 is performed in order to generate signals for recalculating the address of the buffer memory 5 when reading information from memory 5 to node 11 for transmitting it to the slave.

Node 6 (figure 5) is designed for time synchronization of all nodes and elements of the device. The goal of this node is to incorporate into the execution of the algorithm of functioning of the device the corresponding node, which allows to introduce into the technical solutions of the device the elements of regularity (nodes 8, 10, 11)

5 is a reduction in the hardware of a device with rigid hardware logic. Part 6 includes a register 67, which sets the appropriate mode of operation of the device. The mode of operation of the device is determined by

0 elements and triggers 60-66, 68, 69 and input signals of node 6. The mode is set using the CO clock signal (12.1), which synchronizes the setting and resetting the corresponding mode. Register

5 70 is intended for recording indications coming from a computer channel, and together with a counter 81 (a binary counter with a decoder at the output) determines the stage of the current indication. Since the instructions (Set the address of the BP, Start the floor, Erase unprotected to the address, Program tab, Repeat to the address), coming from the E VM, have different formats (instruction code, address bytes, symbol), the difference between the signals from the register 70 and counter 81 provide stepwise execution of each indication. At the end of the execution of the instructions, a signal is generated. The instruction is executed (138.11), which restores the interrupted data reception sequence.

Node 8 (FIG. 3) executes commands from the computer and requiring processing of the transmitted information. So trigger 31

5 The start field is set when the attribute (characteristics) field is read from the buffer memory 5. The set trigger 31 generates the Interrupt signals (135.2) and the formation of the indication (135.1), by which the data transmission is suspended in the node and the indication code is issued to the computer channel. Thereafter, the analysis of the contents of the memory 5 is resumed. The triggers 32, 33, 34 are intended to provide instructions. Set the BP address and Erase unprotected address. These indications are generated if during reading the information from memory 5 a zero information code or an attribute with the characteristic of a modified field was detected. If, when transmitting information from the buffer memory 5, a zero code was read (the signal arrives on line 150.1), then the trigger 32 will be installed, which generates a signal to generate an indication. Then, the contents of the buffer memory are analyzed until an indication code other than zero is found. When a code other than zero is found, the flip-flops 33, 34 are set with the aid of logic elements 26, 27, 28, as a result of which the signal is generated.

By a command from the computer to read the modified, only the information of the modified fields contained in memory 5 should be transferred. For this purpose, in node 8, the attributes contained in the PD are analyzed. Prior to the analysis, a trigger 32 is set based on a signal 133.1. Read the modified field. When viewing memory 5, a signal of an attribute of a modified field is output from it and through line 150.1 enters node 8. After this, triggers 33, 34 are set, which take off the signal Formation of an indication, and node 3 sends a code and bytes to the address of the computer to the channel. . A trigger 30 is set to set the Read / Write information to memory 5. This trigger is set from node 3 by a signal of 133.4, as well as by the receipt of signals Attribute (150.1) and Information BP 2 bit (150.3), which indicates that The protected floor attribute is read and further entry in this field is prohibited.

Node 10 issuing commands and addresses (figure 2) generates command codes and addresses to the slave. The node 10 consists of a priority scheme 14, which generates the address of the slave when it receives a service request. The circuit 14 generates the three-bit address of the higher-priority VU, transmits it to the input of the register 17 of the address, and also generates an Input signal, in the register 16 the command code is read Read the manual input, which through the multiplexer 18 enters the interface buses - T to the VU input. The multiplexer 18 also provides for the transfer of information from memory 5 to the VU (by the Enter command) and from the VU to the memory 5 (by the commands Read manual input and input). The decoder 19 commands generates signals 137.1-137,4, corresponding to the executed commands in the interface - T. These signals are necessary to control the node 11.

The node 11 is used to implement the communication algorithm between the device and the WU via the T interface (Fig. 4). Node 11 generates signals OBR (trigger 54) and SI-B (triggers

49, 50). The OBR signal is intended to indicate to the slave that the device is ready to operate on the current command from the slave. The SI-B signal indicates that the device is configured to be transmitted to the slave (on the Output command) bytes

0 information and received a byte of information on the VU (when executing the command Read manual input and input). The trigger 54 is set after the installation of the trigger 48 (trigger Issue command), which indicates that

5 on the information buses of the interface - T is formed the command and address to the slave. Flip-flop 54 is reset after the transfer of the entire BP contents is complete, i.e. the signal 152 arrives from node 8, or after the signal is removed from the CCT from the control unit (reset trigger 43). A trigger 49 operating in the mode of inputting information into a power supply unit (signal Input 132.7) is set when a signal SI-U (trigger 44) arrives from the control unit (signal SI-U indicates the presence of

5 data buses from the slave) and recording information in the PSU (as indicated by the clock signal 12.5). Trigger 49 is reset after a CI-U signal has been removed from the control unit. The trigger 50 operates in a mode for inputting information from a buffer layer. Its installation is performed according to the signals Output (137.3) and Output Byte (133.2). The trigger 50 is reset after receiving the SI-Y signal. The trigger 44 in the output mode indicates the receipt of a VU byte of information. The flip-flop 50 is reset after resetting the SI-V signal. Trigger 51 Write and read element 52 generate signals to node 3 to perform respectively write and read information byte from

0 BP to WU and to BP from WU. Triggers of the 39 Byte status and 40 Byte of the updated state are used to write the current status byte and the updated state of the slave state to the service memory area.

Claims (1)

5 claims A device for interfacing an I / O channel with a subscriber containing a buffer memory, the first information input and the first output of which are connected respectively to the first output and the first information input of the data multiplexer, the communication unit to the channel, the group of information inputs and the output group of which are relevant 5 groups of inputs and output devices for connecting to groups of information control inputs and output of the I / O channel, and the first information input and the first, second and third outputs are connected respectively to the first output by the first control and information inputs of the block of information registers and the second information the data multiplexer input, characterized in that, in order to increase the speed of the device, the address multiplexer, command execution control node, operating mode storage node, instruction decryption, command issuing and address node, subscriber trigger node and information decryption node, the second output and the control input of the information register block are connected respectively to the first input of the condition and the first output of the command execution control node, the second , the third and fourth outputs of which are connected respectively to the control inputs of the Ydres multiplexers and data and the first control input of the storage node of the modes, the third output of the information register roll is connected to the first information passages node storing node operating modes and issuing commands and addresses, first output control input of which is connected to the clock sootvetst- yenno ,; the input and first output of the node of communication triggers with the subscriber, the groups of inputs and outputs of which are the corresponding groups of inputs and outputs of the device for connection to the groups of control outputs and inputs of the Subscriber, the second output and the third information input of the data multiplexer are connected respectively to the first information the input and the second output of the command and address node, whose input and output groups are respectively the device input and output groups for connecting to the information output groups and the input subscriber and the second controlled The liaison input is connected to the control inputs of the information decryption node, the instruction decryption node, the trigger trigger communication node with subscribers and the first output of the operation storage node, the second output connected to the second command input of the command execution control node, the first and second information inputs of the address multiplexer are connected respectively, with the second inputs of the data multiplexer and the operation storage unit, the second control input connected to the output of the indication decryption node, whose information input connects It is connected to the second output of the data multiplexer, the first output of the address multiplexer is connected to the address input of the buffer memory, the output and control input of which are connected respectively to the first output and the information input of the information decryption node, the second input connected to the second information input of the operation storage node and the third the condition input of the command execution control node, the fourth and fifth condition inputs of which are connected respectively to the second input of the address multiplexer and the second output of the trigger node in connection with the subscriber, the first and second information inputs of which are connected respectively to the third outputs of the address multiplexer and information decryption node, the clock inputs of which and the clock inputs of the trigger node of the communication with the subscriber, the command execution control node and the operation storage node device, the third information input of the storage mode of operation is connected to the second output of the node triggers communication with the subscriber, cm with ifi O) {Ј Initial sample completed successfully Execute the command READ MANUAL INPUT (MF RV) Team midrange RV run ycnejfc but Yes Run the ENTER command (BB) RVV NVIINNNNNNMNVN MKFNN VNYaMMVMNMM Issue command sun Set block loading indication 5 Jl I Prepare the device to work with the channel v Run the DIAGNOSTICS command I Set byte state pointers FIG. 7 The device is ready to receive information from the channel Receive byte information from the channel Write byte information in 1 block 5 To process the received block of information, to prepare for receiving the next block of information To process the accepted instruction according to the corresponding algorithm. Set the appropriate pointer in the byte of the updated state Remove channel mode Device g.tavo to issue ife | 1 channel per command ZHATT16DIFSHYUVAVDOE G Analyze the sod block 5 for. "Riding Stop working with channel 1 Issue to the channel pointers of the status byte of the device KK, EUN ;at , : y (TA) Give the channel an instruction INSTALL BUFFER'S ADDRESS FIG. 9