SU1251093A1 - Interface for linking electronic computers - Google Patents

Abstract

The invention relates to the field of computer technology and can be used in computer complexes. The aim of the invention is to expand the class of tasks to be solved, and the expense of organizing the exchange between a computer with a bus interface and a specialized computer. The goal is achieved in that the device that contains the initial transceiver unit, the communication unit, the decoding unit of the control signals of the first computer, the address decoder , the prereggean block, the multiplexer and the status register, the encryption block of the interface signals of the second computer and the parity check block are entered. 1.z.p, f-ly, 13 ill., 3 tab. W go: l

Description

one

The invention relates to computing technology and can be used in multi-machine computing complexes and computer networks,

The aim of the invention is to expand the field of application by interfacing different types of computers,

FIG. 1 is a block diagram of the device; FIGS. 2-10 are functional diagrams of a channel transceiver unit, an address decoder, a control unit decryption unit of the first computer (computer 1) of a second computer interface signal encryption unit (computer 2), a state register, a multiplexer, a parity unit, an interrupt unit and a communication unit, respectively; FIG. 11 shows time diagrams of operation of the device; FIGS. 12 and 13 show structural diagrams of communication between the device and. COMPUTER 2 in cases of using as a communication unit of a duplex register or fast data transfer module (MBDC). ,

Us-trivstvd (FIG.) Contains block 1 channel transceivers, address decoder 2, block 3 of control signal decoding of computer 1, block 4 of encryption of interface signals of computer interface status register 5, multiplexer 6, parity check block 7, interrupt block 8, block 9 communication (exchange).

The device provides interface, for example, an EJ | computer-60-type computer (COMPUTER I) with a SM-1 mini-computer (COMPUTER 2).

The channel transceiver unit 1 (Fig. 2) is designed to receive or transmit information. To the computer channel 1 and consists of four main transceivers 10-13. These transceivers are in the mode of receiving information from the computer 1 (OUTPUT mode). - formations in computer 1 transceivers are translated by a low signal level Prd.

The address decoder 2 (FIG. 3) decrypts addresses when exchanging information and contains the elements AND 14, NOT 15-21, AND-NO 22, NOT 23, trunk receiver 24, elements AND-NOT 25, and OR-NOT 26. At the inputs decoder 2 receives the address signals of the AOO, 05-12 and the channel signal KVUN, If the received address matches the address of the device mates 251093

five

S 5 20 25

, thirty

Q j

3550

55

The decoder sets the signal to the DEVICE SELECTED,

The control decryption unit 3 (Fig. 4) performs the decoding of the commands and generates the corresponding control signals. Block 3 contains a group of triggers 27, a group of trunk receivers 28-31, elements HE 32, OR 33, 34 and HE 35, decoder 36, element HE 37, trunk transmitter 38, elements HE 39, AND 40, 41, HE 42-45 , trigger 46, elements AND 47 and OR 49-50, diode 51, capacitor 52, elements AND-NOT 53 and And 54, main transmitter 55. Depending on the combination of inputs to the signal inputs, unit 3 generates the corresponding control signals. Possible combinations of signals are given in Table 1 and 2. In block 3, the triggers 27, by the XIAN signal, memorize the signal DEVICE SELECTED, as well as the value of bits AO 1-03. The values of these bits are indicated in the 16-bit word, the meanings of which are given in Table 1,

According to the KVVODN and KVYVN signals, the decoder 36 decrypts the signals received at its inputs and generates control signals depending on the values of AO1-03,

Trigger 46, based on the XIAN synchronization signal, depending on the value of bit A04 (Table 2 /) generates the WED-K and WED-K2 signals,

These signals determine which of the two possible channels of block 9 will exchange information. The address signal A04, as well as the input signals O and B trigger 46 and the element OR 49, 50 form the signals Adr. O and Adr, 1, which are received in block 6.

On any of the signals at the inputs of the element OR 33 (Input O, Input 1, Control, 0, Control, 1) And 54 element forms the transmission signal Prud and from the output of transmitter 55 the synchronization signal of the passive device KSIPN is recorded. The Upr signal, 2, is overhead.

Block 4 of the encryption of the interface signals of the computer 2 (Fig. 5) contains the first delay node consisting of an element 56 and diode 56-1 and a capacitor 56-2, 1 elements OR NOT 57-59, element D-SHI 60, the second node delay 3

And from the diode 61 and the capacitor 62, the elements And 63-66, the element is NOT 67. The block D is used to generate signals that control the exchange of information through the pair of 2K, According to the signal Prd and depending on the incoming signals (Conclusion, 1 , Input 1, Input 2 Out, 2, Control.O, Control.1) the corresponding 2K signals are formed: PSB-K, PR-K, VD-K, VP-K, OST-K, OSB-K for input commands output.

The state register 5 (FIG. 6)) contains elements NOT 68-71, elements AND 72-75, element OR 76, triggers 77-84, elements OR 85, 86 and el-elements AND 87-90, produces the signals of the state of the interface device during the exchange.

The first inputs of the And 72, 73 elements receive the enabling signal O.O., and the second inputs the corresponding sampling signal (WED-K1 or WED-K2), indicating which channel of the block 9 will be used for information exchange.

If there is a high level of PDE (resolution of fault by mistake), the trigger 78 or 80 remembers the resolution signal and the MOSH1 or MOSH2 signal is generated for blocks 6,8.

In a similar way, the interruption resolution signal is ready on the trigger 71 -k 79 on readiness and the MGT1 or MGT2 signal is generated for blocks 6, 8 at a high level of bit D06.

Triggers 81-84 remember the end-of-operation signals and the parity error signal when the corresponding signals are received at the inputs of the HE elements 70 and 71, the AND elements 72-75 and the OR element 76, as well as the OIUl signal from block 7. The signals KOP1 or COPA are generated. Opsh or opsh. The elements OR 85 and 86 form intermediate interrupt signals ОSH01 or ОSH02 depending on the signal of the WED-K1, WED-K2 sample). Elements 87-90, by the input signal O and with the corresponding signals at the inputs, form an error signal ОШ1 or ОШ2 and a ready signal ГТ1 or ГТ2 in block 6, depending on the signal of the sample (WED-K1 or WED-K2).

Multiplexer 6 (Fig. 7) contains elements AND 91-98, elements HE 99- 106, selector-multiplexers 107

5 o

 five

0 25

thirty

five

0 5 0

five

;

0934

110 and selects information and transmits to computer channel 1.

The multiplexer has 4 modes of operation, depending on the signals Adr.O, Adr.1 and Input 1 received at its inputs (Table 3).

The first mode is reception from the 2K interface: ADR..O and Adr.1 - the zero level. Input 1 - single level. Information from the 11INOO-15T buses through the elements AND 91-98, the elements NOT 99- 106 and the selectors 107-110 enters through the block 1 into the channel of the computer 1.

The second mode - reading register 5: Addr. O - single level, Addr, 1 and Input 1 - zero levels. On computer channel 1, multiplexer 6 sets the contents of state register 5. The third mode - reading register 5: Adr.1 - unit level, Adr. O and Input 1 - zero levels. Similar to the second mode, the contents of register 5 are transmitted when exchanged via another channel of block 9. L

The fourth mode is reading the interrupt vectors: Adr. O and Adr.1 - single levels. Input 1 - zero level. The interrupt vectors (the address of the processing program) are set to the channel of the computer 1 via block I by means of signals B (D07), VO (D02), B, 1 (DOS).

The parity check block 7 (Fig. 8) performs the control of the correctness of information reception and the formation of check bits during transmission. Block 7 contains parity bit elements 111 and 112, element R1GSH 113, elements AND 114 and 115 ,. parity bit generation elements 116 and 117 and comparison circuits 118-120.

In the mode of receiving information from computer 2, via block 9, it enters the SHNOO-15T buses to elements 116, 11 7 and check bits KPO-T and KP1-T to the inputs of comparison circuits 118 and 119, respectively. Elements 116 and 117 perform byte control and form internal check bits KPO and KP1, which are compared with comparison circuits 118 and 119 with check bits KPO-T and KP1-T. The error signal at the CWP parity is generated if the total number 1 in any byte (info + check digit) will be even.

in the mode of information transmission in computer 2, the formation of check bits is necessary, since computer 1 does not form such bits. This function is in block. 7, elements 111 and 112 are performed. From the computer channel 1, through block 1, information on the 1 NNR-15K buses enters the elements 111 and 112, the inputs of the element 11 1 receive the high byte f and the inputs to the element 112 are the low byte, the Elements 111 and 112 form check bits, and the signal Kvy-K and KP1-K is set at their outputs at the outputs of the check bits.

Interrupt unit 8 (FIG. -8) performs the operations of capturing the channel of the computer 1 and interrupting the program and includes a trunk receiver 121, elements AND 122-128, triggers 129-132, elements AND-.HE 133-139, trunk transmitter 140, element AND-OR-NOT 141 elements NOT 142, trunk transmitter 143, elements NOT 144-147, elements OR-NOT 148-151, and triggers 152-155.

In accordance with the input signals, block 8 generates channel signals KPRO and KTPR, as well as signals B, BO, B1.

In the initial state, the triggers 129 132 are set up in such a way that they allow the passing of the HRSG interrupt provision signal and the output via the transmitter 140 of the RDSPP signal to provide the signal to another device connected to the computer channel 1.

On the readiness signal of the TRP-T1 (information is exchanged through the zero channel of block 9), the trigger 152 switches and the GT1 signal is set to block 5. When the interrupt is enabled, MGT1 through the AND-OR-NE 141 element at the output of the transmitter 143 sets the interrupt request signal KTPR, which: enters the computer channel 1. At the INP signal, block 3 triggers trigger I29, blocking the formation of the CCTPRO signal (propagation KS1R1) .

The KTPR signal of the computer 1 exposes the CAT 1 signal to the channel. At the inputs of the NAND 133 element, single levels are set, which causes the formation of the B signal on the I –NE 137 element and the input signal O switch 10

25

2510936

trigger 152 to its original state.

Upon the readiness signal of the TRP-T2 (the exchange is carried out through the first channel of block 9), the trigger 154 switches and the GT2 signal is set to block 5. When the interrupt is enabled, the MGT2 generates a KTPR signal and, via the ENTER signal, triggers 131 toggle to block the formation of the MSTD signal.

The signal KPR1 at the inputs of the element AND-NOT 135 is set to single levels, which also causes 15 formation of signals B (element AND-NO 139), and the signal Input O causes the trigger 154 to return to its initial state.

The processing of the error signals OLL1 and 20 01Ч02 occurs in a similar way. According to the signal ОSH01, the signals of the vector B and B1 are formed, and by the signal OSH02 the signals of B, B1 and VO are formed.

 The communication unit 9 is intended for receiving, storing and transmitting information to the communication link with the computer 2. As the communication unit 9, serially starting devices from the ASBT-M CM nomenclature can be used, for example, duplex; register A49I-3M or fast data transfer module MBPD A723-1.

When using a duplex register, the communication of the block 9 with other blocks of the device with the computer 2 is carried out over a single channel; when using MBDC, over two channels: the transmission channel (zero channel) and the reception channel (first channel), and the channel number is set by WED-C signal .

FIG. 10 shows the scheme of connecting the device to the computer 2, when a duplex register is used as the block 9 (work on one channel). In this case, the exchange unit 9 contains the output 156 and input 157 registers, the element OR 158, the triggers 159-161, the elements AND 162-166,

A similar duplex: register in computer 2 contains the input register 167, the element OR 168, the triggers 169- .171, the elements AND 172-176 and the output register 177.

Communication between block 9 and computer 2 is via inputs 178 and outputs 179 of the device.

7

The device works as follows.

The computer 2 exposes information to the IINOO-15K, KRO-K, KP1-K buses, and when the signals of the VD-K, PSB-K and

. FBG-K records it in the upper register 167. This information is fed to the input of the input register 156 of block 9. The signal from the computer 2 VP-K at the output of the trigger 170 generates an VP-I signal, which is received as a GT-P signal (FIG. ten). This signal at the output of the trigger 159 establishes the signal of the TRP-T, informing that the output of the output register 156 received information. The device processes the TRP-T signal and, by coincidence of the PR-K and VBR-K signals, it reads it from register 156. After that, the device releases the VP-K, which is used for recording the TRP-T signal at the trigger output 159 and sets the signal VP-I at the output of the trigger 160. This signal of the computer 2 receives as a signal GT-P, confirming the readiness of the device for the next exchange cycle.

The exchange of information between the computer 1 and the computer 2 through the device is carried out in 16-bit words with a readiness query or using program interruption means. The exchange operations and control over the state of the interface device are carried out by register 5. Signals produced by register 5 are received through multiplexer 6 and block 1

In the computer channel 1 and in the form of 16-bit words.

The interface device operates in two modes: INPUT mode and OUTPUT mode.

Sharp INPUT (timing diagram in Fig. II), In this mode, information is transferred from computer 2 to computer 1.

The computer 1 in the address part transmits the address of the interface device as well as the KVUN signal to the decoder 2 via block KDAOO-15N, and the address decoder 2 decodes the received information (AEO, 05-12 / and generates a signal SELECTED, which arrives at block 3, 150 after not after the address of the computer I issues to block 3 a CSIAN synchronization signal, according to which unit 3 memorizes the value of the signals of AO1-03, after which the computer 1 removes information from the KDAOO-15N lines

0938

clears the KVUN line and sets the HFSP signal to indicate the readiness to receive information from the interface device.

Block 3, having received the signal XIAN and KVVODN, generates a sampling signal (WED-K1 or WED-K2) at the corresponding value of the signal A04 (FIG. 4) and the signals Input 1 and Input 2, as well as the transmission enable signal Prd. According to the Input 1 signal, the block A exposes to the block 9 a read enable signal of the PR-K. If there is a WROB-K and PR-K signal, the block .. 9 reads the information from the computer 2 through the register 156. This information is received through the multiplexer 6 via the DAED buses -15 to block 1, which, in the presence of a transmission enable signal, PdP, exposes this information to computer channel 1. Simultaneously, with a delay relative to the K KVODN signal, block 3 generates a KSIPN signal, which notifies computer 1 that the information is set to the channel. The computer 1 receives the signal CSIPN, receives data from the channel and removes the signal KVODN. Block 3 removes the CSINN signal completing the data transfer. The computer 1 removes a xsian signal from the leading edge of the CSIN signal, completing the channel INPUT cycle.

OUTPUT mode (timing diagram in Fig. 11). In this mode, information is transmitted from computer 1 to computer 2.

The computer 1 sets the address of the interface device and the CVID signal on the line KDAOO- 15H. Decoder 2 addresses decrypts the received information and generates a signal DEVICE SELECTED, which permits the operation of the block

3. The computer 1 after 150 is not after the address is received, the signal of the XIAN is used, according to which unit 3 memorizes the values of the signals A01-03 and generates the signal of the WED-K1 (WED-K2) signal,

The computer 1 removes the address, clears the KVUN line, after which the data is placed on the KDAOO-15N line and: after 100 does not give the signal KWINOW. According to this signal, block 3 generates a signal for transmitting transmission of Prd and signals PEL.1 or Vyv.2, which enter the block

4. Upon the arrival of these signals, block 4 sprinkles the PSB-K signal into block 9, which clears the input register 157, and the VD-K signal, which is used to write data to the register 157 from the output of block 1 (111INOO-15K) and check bits (KRO-K, KP1-K) from block 7. In addition, block A exposes to block 9 a VP-K signal informing the computer 2 that the information is exposed to the Tires-off bus 15I. Block 3 sends to the computer 1 a CSITN signal, meaning that the data is received by the interface device. The computer 1, having received the signal of the CSINN, clears the non-KVYVODN line after 150, and after 250 it does not get the signal of the KSIPN computer 1 and removes data from the KDAOO-15I line. The interface device removes the CSIDN signal, and the computer 1 removes the XIAN signal, thus completing the output cycle.

The exchange of information between the computer 1 and computer 2 can be conducted on the initiative of any computer. Obien starts with issuing a VP-K signal, which is initiated by the exchange unit into the GT-T readiness signal (FIG. 10). Upon receiving the GT-T signal, any computer switches to the control word receiving mode, in which the exchange type is encoded (reception or information), Upon receipt of the control word, the computer deciphers it and goes into either receive mode or in the mode of information output

Claims (2)

Formula invented and 1, A device for interfacing two electronic computing machines (computers) containing a channel transceiver unit, the input / output of which is connected to the information input / output of the first computer, the information input of the channel transceiver unit connected to the multiplexer output, and information output i - with the first group. information inputs of the communication unit, with the first information input of the register, the first input of the address decoder and the first group of inputs of the decoding unit of the control signals of the first computer, the second group of inputs and the first group of outputs of the decoding unit of the control signals are connected respectively but with groups of inputs and outputs of synchronization of the first computer, and the first output and the second group of outputs of the decryption block of control signals are connected respectively to the control input of the channel transceiver unit and the second information the main state register input, the first and the second The output groups of which are connected respectively to the group of information inputs of the interrupt unit and the first group of information inputs of the multiplexer, the control input and the second group of information inputs of which are connected respectively to the second output of the control unit decryption of the first computer and the group of outputs of the interrupt unit, the enable input and the output the request of which is connected, respectively, to the output of the resolution of failure, and the input request of the interruption of the first computer, and the reset input of the interrupt unit to the reset register of the state register and the third output of the decoding unit of the control signals of the first computer, the first input of the decoder connected to the output, the addresses strobe the input of which is connected to the output of the device select signal of the first computer, the second group of information inputs of the block The connections are connected respectively with groups of informational outputs and inputs of the second computer, characterized in that, in order to expand the scope of application by interfacing different types of computers, a ciphering unit is introduced into it the interface signals of the second computer and the parity checker, the information input group, the information input and the resolution of the encryption block of the interface signals of the second computer are connected respectively to the third output group and the third and first outputs of the decryption block of the control signals of the first computer, and interface signals of the second computer - to the first group of synchronization inputs of the communication unit, the second group of synchronization inputs and the group of synchronization outputs of which are connected to the sync groups oniziruyuschih outputs and inputs of the second computer, the second group of information outputs communication connection unit is connected to the third group of information inputs of the multiplexer, the first group of information inputs and the first input of the check bit of the parity check block and the third information input of the status register, the fourth information input of which is connected to the output of the error signal of the check block the second group of information inputs and the output of the control ramp of which are connected respectively to the information output of the channel transceiver unit and the first group of information inputs of the communication unit, and the mode input to the fourth output of the decoding unit of the control signals of the first computer, the second input, The output and the second group of outputs are connected respectively to the group of outputs, the blocking input and the synchronizing input of the interrupt unit, and the third group of outputs is connected to the resolution input of the communication unit, the output is ready The bones of which are connected to the interrupt request input of the interrupt unit, 2. The device according to claim 1, characterized in that the decoding unit of control signals of the first computer contains four main receivers, the inputs of which form the second group of inputs of the block, two main transmitters, the outputs of which form the first group of outputs of the block, the group of triggers and trigger, information the inputs of which form the first group of inputs of the block, the decoder, the first input of which is the first input of the block, four OR elements, a delay node, five AND elements and eight NOT elements, the output of the first main circuit It is connected to the trigger and trigger triggers of the group, the output of the second trunk receiver is connected via the first element NOT to the reset inputs of group triggers and the third output of the block, the output of the first OR element is connected to the first input of the second element OR, the output of the third trunk receiver is connected to the second input the decoder, the third input connected through the second element is NOT to the output of the fourth trunk receiver and the second input of the second element OR,. the first output of the decoder is connected via the third element NOT to the input of the first main transmitter, the second and third outputs of the decoder 51093 12 connected respectively to the input of the fourth element NOT and the first inputs of the first and second elements I, the second inputs of which are connected to the output of the first trigger of the group, the first inputs of the third and fourth elements I connected to the direct and inverse outputs of the trigger, respectively, the first, second inputs first About element OR are connected respectively. through the fifth, sixth elements of the NOT with the fourth, fifth outputs of the decoder, the sixth and seventh outputs of which are connected respectively to the 5 inputs of the seventh and eighth elements of the NO, the output of the last and the output of the fourth element are NOT connected respectively to the third and fourth inputs of the first element OR, the first 20 inputs of the third and fourth elements OR are connected to the second input of the unit, the second inputs are connected respectively to the outputs of the third and fourth elements AND, the second inputs 5 of which are connected to the output of the fifth element NOT, the outputs of the fourth element NOT and the third and fourth elements OR form the second output of the block, the output of the second element OR 0 is connected to the first input of the fifth AND element and through the delay node to the input of the second main transmitter and the second input of the fifth AND element whose output is the first and the second output of the block; the outputs of the second and third group triggers are connected respectively to the fifth and sixth inputs of the decoder, the eighth output of which is both the direct and inverse outputs — Q turns of the trigger and the outputs of the fifth, sixth and seventh elements brazu- dissolved vghodov second group unit, second, fifth outputs of the decoder, the outputs of the first and second AND gates,. 5 the output of the first group trigger and the output of the eighth element do NOT form the third group of block outputs, the third output of the decoder and the output of the second. element And form the fourth output of Q block, the output of the third trunk receiver is the fifth output of the block. O - Read register 5 Record in the register 5 Reading register 156 block 9 O1 about + Control of VBRO-K, VP-K Confirmation readiness to perform the next cycle O1 O1 1 + about 1 1o 1o 1 + 83, 83 in register 5 Enter 2 VBRO-K, Read register of PR-K, VP-K, 156 block 9 s (WB} -K, PR-K with the notification of the computer 2 VP-K) on readiness for performing the next cycle Conclusion 2 VBRO-K, Record in the register PSB-K, VD-K, 157 of block 9 with VP-K, (VBR1-computer notification 2 K, PSB-K, on readiness for VD-K, VP-K) the following cycle Writing in register 157 block 9 u r four O & T A / "g KffjwxoM 7.9 Ajt 1531K r / 5Agg   II I-J tfM II I 1 fishing - 11 ShZh M  W-1-ff  . five , to SjKiKtj 3 guv S & GT-I Fnlrer g 2S KCBHtH. 13 Mr.Spoe kuan X and 8jvn / b veo X BtitM 31 -shrp Pr8 cnpn AvtsO vtbttoe "PvitAi to stop ft r 39 t f l Bto31 "D25u X VVVZG KSfloKtiS Scheme 33 VM Upr, 3 Yn & o flap tul.1 .. Kul5ka 17 Input About to Shred S, 8 scheme, 7W  block 5  Ksjmyitf hell  f " ZPR.O to 33 A / L K1l6kd S Jfnp.} / Hl / ty Cxef 33 qtg ") VP-K "about demand R ggg-x I owl l- fn i vshg o - uh 89 Yy . Of S / UPZ 6 a7 th "svZ KfJIOKy 1 : "N Fig.12 Editor I.Rybchenko Compiled by V. Vertlib Tehred I. Gaidosh Order 4412/46 Circulation 671 Subscription VPIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Razdiska nab. 4/5 TT Troichvodstveneno-printing company, Uzhgorod, st. Project, 4 . 77 Proofreader M. Demchik